9results about How to "Reduce packaging process" patented technology

The invention discloses a packaging machine capable of metering and supplementing materials twice, and belongs to the technical field of packaging equipment.The packaging machine comprises a first conveying belt, a bag conveying mechanism, a second conveying belt and a filling mechanism, the bag conveying mechanism is arranged on one side of the first conveying belt, and the first conveying belt is used for conveying packaging bags to one side of the bag conveying mechanism; a second conveying belt is arranged on one side of the bag conveying mechanism, and one end of the second conveying belt is close to the bag conveying mechanism; the packaging bag filling device has the beneficial effects that through the design of the clamping mechanism, stable fixing of a packaging bag is achieved, toppling or shifting of the packaging bag in the filling process is avoided, through the telescopic action of a first air cylinder, a clamping suction cup can firmly clamp the packaging bag, it is ensured that the packaging bag is kept stable in the filling and metering process, and the packaging bag filling device is convenient to use. The risks of material leakage and packaging bag damage are reduced, the stability and safety in the packaging process are improved, and therefore the packaging quality and the production efficiency are improved.

The present invention discloses a MEMS inertial sensor chip module and a preparation method thereof. The MEMS inertial sensor chip module of the present invention comprises a housing, wherein the housing is respectively fixed with a PCB board and a metal support column, wherein a MEMS inertial sensor chip assembly is supported on the metal support column, and the connection terminals on the MEMS inertial sensor chip assembly are mutually connected with the connection terminals on the PCB board through metal wires. The present invention does not require a primary packaging process, greatly reduces the packaging and integration costs, reduces the integration volume, avoids the thermal stress involved in surface mounting, can also achieve rapid heat conduction, can maintain various performance indicators of the MEMS inertial sensor chip level, can improve the application restrictions of the prior art on the MEMS inertial sensor chip, and avoids the influence of the primary packaging or secondary packaging thermal stress on the system integration application.

An embodiment of the present invention provides a virtual-reality collaborative platform supporting remote wireless communication link testing and a communication test platform supporting remote testing. The communication test platform includes: a communication test device and a local server, which establish a first communication connection based on physical layer communication between each other, and the local server is configured to provide a remote interface to establish a second communication connection based on a persistent communication protocol in response to a request for remote testing initiated by the remote server; during the remote test, the communication test device sends the communication link measurement data regularly collected by the data probe embedded therein in an orderly manner via the first communication connection according to a predetermined reporting cycle, and the local server sends the received communication link measurement data to the remote server via the second communication connection in real time. The present invention can transmit the communication link measurement data to the remote server in a real-time, stable and efficient manner to reduce data blocking and improve the display effect and on-site experience.

The invention provides a vertical cavity surface emitting laser and a preparation method thereof, and relates to the technical field of semiconductor lasers. The vertical cavity surface emitting laser comprises a substrate and a first sub-N-type DBR layer arranged on the substrate, the surface, away from the substrate, of the first sub-N-type DBR layer is divided into a plurality of areas, each area is provided with a second sub-N-type DBR layer, an active layer and a P-type DBR layer in a stacked mode, the outer contour of the surface of the second sub-N-type DBR layer is located in the outer contour of the area where the second sub-N-type DBR layer is located, and the P-type DBR layer is located in the active layer. The outer contour of the surface of the active layer and the outer contour of the surface of the P-type DBR layer do not exceed the outer contour of the surface of the second sub-N-type DBR layer. According to the vertical cavity surface emitting laser, equivalently, a plurality of sub vertical cavity surface emitting lasers are simultaneously formed on one substrate, and each sub vertical cavity surface emitting laser can release laser of one wave band, so that the vertical cavity surface emitting laser can release laser of multiple wave bands, and the cost is relatively low.

The invention provides a transistor device and a manufacturing method thereof. The transistor device comprises a channel layer, a barrier layer, a grid electrode, a first electrode, a second electrode, a first connecting block, a second connecting block and a dielectric layer, the barrier layer is stacked on the channel layer, the dielectric layer is stacked on the barrier layer, and the grid electrode is located on the dielectric layer; the contact surface of the channel layer and the barrier layer is provided with two-dimensional electron gas, the two-dimensional electron gas comprises an active region and a resistance region which are spaced from each other, the resistance region is of an annular structure surrounding the active region, and the resistance region is provided with an opening; the first electrode and the second electrode penetrate through the dielectric layer and the barrier layer to be in contact with the active region, the first connecting block and the second connecting block penetrate through the dielectric layer and the barrier layer to be in contact with the two sides of the opening of the resistance region, and the first connecting block is electrically connected with the grid electrode.

The utility model discloses a packaging structure of a light quantum chip. The packaging structure of the light quantum chip comprises a first heat dissipation substrate; the semiconductor cooler is located on the first heat dissipation substrate; the first heat dissipation substrate is located on the semiconductor cooler, the second heat dissipation substrate is located on the semiconductor cooler, the PCB is located on the first heat dissipation substrate, and the second heat dissipation substrate is electrically connected with the PCB; the light quantum chip is located on the semiconductor cooler, the at least two optical fiber arrays are located on the semiconductor cooler and the first heat dissipation substrate, and the light quantum chip is located between the two optical fiber arrays and is in optical coupling connection with the two optical fiber arrays; the PCB comprises an FPC (Flexible Printed Circuit) connector; the FPC connector is welded on the reverse side of the PCB, the FPC connector is in line connection with the front side of the PCB, and the FPC connector is used for providing a driving electric signal for the light quantum chip. According to the utility model, the temperature of the light quantum chip can be conducted out to ensure the stability of the chip; the operation frequency of the technological process is reduced, and the product packaging reliability is improved.

The invention relates to the technical field of composite materials, and in particular to a waterproof and fireproof bimetallic thermostat packaging shell and a packaging process thereof; the invention uses epoxy resin as the packaging shell of the bimetallic thermostat, thereby reducing the packaging process and the time cost, and in order to enhance the water resistance and fire resistance of the epoxy resin, the invention also performs a blending modification treatment on the epoxy resin to prepare a flame-retardant modified carbon nanotube, grafts a carboxyl group on the carbon nanotube, and utilizes the carboxyl group to react with an isocyanate group to generate a free isocyanate group, and then grafts the carboxyl group with a branched phosphorus silicon polymer of an amino group, thereby making the carbon nanotube have certain flame retardant properties, and the free amino group can also be utilized to introduce a silicon-oxygen bond into the epoxy resin, thereby reducing its surface energy and improving the hydrolysis resistance of the epoxy resin, thereby enhancing the adaptability of the packaging shell to various environments.

The invention discloses a data communication method, device and system and a storage medium, and relates to the technical field of Ethernet communication, and the data communication method comprises the steps: firstly obtaining a plurality of data packets generated by an upper-layer application, and then constructing corresponding communication sub-packets according to the data length, the content and the check code of the data packets; and extracting a standard Ethernet frame header, inserting a combined identification field, splicing the communication sub-packets to the identification field in sequence, adding a frame verification sequence to generate a combined packet, and sending the combined packet to a receiving end. And the receiving end executes first integrity check through the frame check sequence, splits the communication sub-packets according to the merging identifier after the first integrity check passes, and executes second integrity check through the communication sub-packet check code to process the effective communication sub-packets. According to the invention, the redundancy overhead is reduced through merging and packaging of multiple small data packets, the equipment compatibility is guaranteed by the standard frame header, the anti-error-code capability is improved through double-layer verification, and the transmission efficiency and the anti-error-code performance of the small data packets can be optimized while the compatibility is considered.