Groove-interconnected wafer level MOSFET encapsulation structure and implementation method

Abstract

The invention relates to a groove-interconnected wafer level metal-oxide-semiconductor field effect transistor (MOSFET) encapsulation structure and an implementation method. The structure comprises a chip body (1-1); a chip source electrode (2-1) and a chip gate electrode (2-2) are arranged on the front surface of the chip body; chip surface protection layers (3) are arranged on the front surfaces of the chip source electrode and the chip gate electrode of the chip body; chip grooves (1-2) pass through the front surface and the back surface of the chip body; circuit layers (4) are arranged onthe surface of the chip source electrode, the surface of the chip gate electrode and the surfaces of the chip surface protection layers (3) and in the chip grooves (1-2); a circuit surface protectionlayer (5) is arranged on the surface of the circuit layer; welded balls (6) are arranged on the surfaces of the circuit layers (4) on the front surface of the chip body (1-1); a back surface metal layer (7) is arranged on the back surface (1-3) of the chip body (1-1); and the back surface metal layer (7) is interconnected with the circuit layers (4). The encapsulation structure with high performance, and a process method which is used for implementing the structure and has high production efficiency and is low in encapsulation cost are provided.

Description

technical field [0001] The invention relates to a wafer level chip size packaging structure and a realization method. It belongs to the technical field of semiconductor packaging. Background technique [0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a field effect transistor that uses electric field effects to control semiconductors. MOSFETs have received increasing attention in recent years due to their characteristic of enabling low power consumption voltage control. The performance of MOSFET, especially the current carrying capacity, largely depends on the heat dissipation performance, and the heat dissipation performance mainly depends on the package form. However, traditional MOSFET packages are mainly in the form of TO, SOT, SOP, QFN, QFP, etc. This type of package wraps the chip in a plastic package, which cannot conduct or dissipate the heat generated by the chip in time, which restricts the performance improvement of the MSOFET. . Moreover,...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the deficiencies of the traditional MOSFET packaging structure and its implementation method, to provide a high-performance trench interconnection wafer-level MOSFET packaging structure and a realization method with high production efficiency and low packaging cost

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