Rear through-hole interconnected wafer level MOSFET (metal oxide semiconductor field effect transistor) packaging structure and implementation method
A technology of packaging structure and implementation method, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of restricting the performance improvement of MSOFET, unable to conduct or dissipate heat from the chip, and increase the size of the device, so as to shorten the interconnection distance, Improve the current carrying capacity and enhance the effect of conduction
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[0024] see figure 1 , figure 1 It is a cross-section schematic diagram of the through-hole interconnection type wafer-level MOSFET packaging structure of the present invention. Depend on figure 1 It can be seen that the packaging structure of the wafer-level MOSFET with post-via interconnection in the present invention includes a chip body 1-1, a chip through hole 1-2, a chip source electrode 2-1, a chip gate electrode 2-2, and a chip surface protection layer. 3. Front circuit layer 4 , circuit surface protection layer 5 , solder balls 7 and circuit layer 6 . The chip source electrode 2-1 and the chip gate electrode 2-2 are arranged on the front of the chip body 1-1, and the chip surface protective layer 3 is arranged on the front of the chip body 1-1, the chip source electrode 2-1 and the chip gate electrode 2-2; The front circuit layer 4 is arranged on the surface of the chip body 1-1, the chip source electrode 2-1, the chip gate electrode 2-2 and the chip surface protect...
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