CMOS image data training system and image data serialization-deserialization simulation detection method

Abstract

The invention discloses a CMOS image data training system and an image data serialization-deserialization simulation detection method, relates to the CMOS image data serialization-deserialization simulation detection method and solves the problem that the data serialization-deserialization is difficult to carry out due to the fact that an uncertain phase relationship exists among transmission channels employed by a CMOS image sensor each time when electrification is carried out. The CMOS image data training system comprises the CMOS image sensor and a data processor. The interior of the data processor is composed of iodelay, an iserdes, data asynchronous FIFO, control asynchronous FIFO, a gearbox, a ram based shifter and a controller. The controller is taken as the core of the CMOS image data training system and is used for controlling various components to work coordinatively. Under the control of the controller, the CMOS image sensor outputs serial graph data and finally the serial graph data is converted into parallel image data with bit width of p through the iodelay, the iserdes, the data asynchronous FIFO, the control asynchronous FIFO, the gearbox 1:2 and the ram based shifter. According to the serialization-deserialization detection method based on simulation provided by the invention, different excitations are generated for different data training phases, thereby realizing different training strategies.

Description

technical field [0001] The invention relates to a simulation detection method of serial-parallel conversion of CMOS image data, in particular to a simulation detection method of serial-parallel conversion of CMOS image data with high resolution and high frame rate. Background technique [0002] Today's CMOS image sensors with high resolution (not less than 10k × 8k) and high frame rate (not less than 20fps) usually use multiple (not less than 32 channels) high-speed serial channels for image data transmission. There is no definite phase relationship between the channels at each power-on, which brings great difficulty to the serial-to-parallel conversion of data. Due to the large number of channels, it is difficult to use the internal DCM such as virtex 2 to delay the sampling data. It is necessary to use the internal integrated IODELAY and ISERDES modules such as virtex 6. In order to meet high-speed applications, it is also necessary to reduce the load of the regional clock...

AI Technical Summary

Problems solved by technology

[0003] The present invention provides a CMOS image data training system and a serial-to-parallel system to solve the problems that there is no definite phase relationship between the transmission channels used in the existing CMOS image sensor every time power-on, which brings difficulties to the serial-to-parallel conversion of data. Simulation detection method for conversion

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