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Packaging substrate and its electronic package and manufacturing method

A technology for electronic packaging and packaging substrates, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., and can solve the problem of the difficulty in effectively reducing the thickness of the overall semiconductor package 1, the difficulty in reducing the thickness of the packaging substrate 1a, and increasing the manufacturing process. Complexity and other issues, to achieve the effect of overall thickness reduction, cost reduction, and simple process steps

Active Publication Date: 2020-04-07
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the conductive hole 13 needs to be mechanically drilled or laser drilled in the core layer 10 to form a through hole 100 penetrating through the core layer 10, and then copper is electroplated in the through hole 100, thus increasing the manufacturing process. the complexity of
[0008] In addition, because the existing packaging substrate 1a has a core layer 10 and at least two circuit layers, it is difficult to reduce the thickness of the packaging substrate 1a, so when the thickness of the packaging substrate 1a is difficult to reduce, the overall semiconductor package 1 The thickness is also difficult to effectively reduce

Method used

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  • Packaging substrate and its electronic package and manufacturing method
  • Packaging substrate and its electronic package and manufacturing method
  • Packaging substrate and its electronic package and manufacturing method

Examples

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Embodiment Construction

[0059] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0060] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "upper", "lower", "first", "sec...

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Abstract

Disclosed are a package substrate and an electronic package and manufacturing method thereof. The package substrate includes an insulation protection layer, a wiring layer buried in the insulation protection layer and not penetrating the insulation protection layer, and a conductive pillar penetrating the insulation protection layer and electrically connected to the wiring layer. Therefore, the present invention Package substrate has only one wiring layer, and does not use the core layer, which can significantly reduce the thickness.

Description

technical field [0001] The invention relates to a packaging substrate, especially a packaging substrate without a core layer, an electronic packaging part and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronics industry, many high-end electronic products are gradually developing in the direction of light, thin, short, small, etc., and with the evolution of packaging technology, chip packaging technology is becoming more and more diversified. The size or volume of the semiconductor package is also continuously reduced, so as to make the semiconductor package thinner and smaller [0003] figure 1 It is a schematic cross-sectional view of a conventional flip-chip semiconductor package 1 . Such as figure 1 As shown, the semiconductor package 1 includes a package substrate 1 a and a semiconductor element 9 . [0004] The packaging substrate 1a includes: a core layer 10; a first circuit layer 12a and a second circuit l...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L21/4846H01L23/49811H01L23/49827H01L23/49838H01L2224/16225H01L2224/48091H01L2224/48227H01L2924/15311H01L2924/181H01L2924/00014H01L2924/00012
Inventor 邱士超陈嘉成林俊贤范植文米轩皞
Owner SILICONWARE PRECISION IND CO LTD
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