Semiconductor package

Abstract

The embodiment of the invention discloses a semiconductor package. The semiconductor package is accommodated into an intermediate layer. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

Description

technical field [0001] The invention relates to packaging technology, in particular to a semiconductor packaging. Background technique [0002] As known to those skilled in the art, there are currently various chip packaging technologies, such as ball grid array (BGA), wire-bonding, flip chip, etc. , for mounting the die to the substrate via joints on both the die and the substrate. In order to ensure miniaturization and multifunctionality of electronic products or communication devices, semiconductor packages are required to be small in size, multi-pin connections, high speed, and high in functionality. [0003] Since the Wire-bonding System-in-Package (WBSiP) technology can increase the capacity of semiconductor packages, the WBSiP technology has been widely used. WBSiP involves stacking multiple chips together and connecting them to each other by wire bonding. However, traditional WBSiP suffers from some problems, for example, the package thickness, the ability to supp...

AI Technical Summary

Problems solved by technology

However, the above-mentioned TSV-based technologies are expensive and involve complex manufacturing processes

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