A dynamic reconfigurable array data path with multi-level cache and its control method
A data path and cache technology, applied in the field of embedded reconfigurable systems, can solve problems such as reducing memory read and write bandwidth, reducing pipeline operating frequency, limiting performance improvement of reconfigurable arrays, etc. Data bandwidth and the effect of improving operational efficiency
Inactive Publication Date: 2018-05-29
ZHEJIANG UNIV
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This will reduce the read and write bandwidth of the memory, which will further reduce the operating frequency of the pipeline
[0006] To sum up, in the process of implementing the present invention, the applicant found that the storage system in the existing reconfigurable data path cannot meet the requirements of high sharing and high bandwidth at the same time, thus limiting the performance improvement of the reconfigurable array
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[0031] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.
[0032] Such as figure 1 As shown, the reconfigurable data path of this embodiment includes a plurality of coarse-grained operator mesh arrays: composed of isomorphic computing unit (PE) arrays and interconnection units between them, between two adjacent rows of PE units Interconnected through a replacement-based network unit; the interface in the data path: used to read the operand from the external memory and send the configuration information to the multi-level cache system; the level 1 cache in the data path: located in two connected Between the PE units, it is used for data caching and data exchange in the internal pipeline of the mesh array, which is implemente...
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The invention discloses a dynamic reconfigurable array data path with multi-level cache and its control method. The system includes a multi-level cache system composed of four levels of cache, a reconstruction control module of the multi-level cache, and The coarse-grained operator mesh array and the interface module in the data path, in which: the multi-level cache system is used to complete data storage, data exchange and data synchronization in the data path under the control of the configuration code; the multi-level cache reconstruction control module Under the control of the configuration code, the mapping control between the read-write variables of the mesh array and the multi-level cache address is completed; the coarse-grained operator mesh array is used to form the link used for calculation, and under the control of the configuration code, according to the data The definition of a flow graph controls its read and write variables. The configurable dynamic reconfigurable array data path with multi-level cache and the method thereof in the present invention have high data sharing degree, large data storage bandwidth, and can improve pipeline and non-pipeline calculation efficiency.
Description
technical field [0001] The invention relates to the field of embedded reconfigurable systems, in particular to a dynamic reconfigurable array data path with multi-level cache and a control method thereof. Background technique [0002] Due to the inclusion of special reconfigurable processing units, reconfigurable arrays maintain application flexibility while gaining performance and power advantages, making them an ideal model for application-specific computing. The reconfigurable array architecture has two characteristics: First, the hardware structure is composed of reconfigurable data paths and reconfigurable controllers. The reconfigurable data path adopts an array structure composed of basic computing units; second, the processor control flow is separated from the data flow. The reconfigurable datapath is used to process the data flow, and the reconfigurable controller is used to execute the control flow to control the reconfigurable datapath. [0003] The reconfigurab...
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IPC IPC(8): G06F12/0897G06F12/0871
Inventor 王珑沈海斌王星朱佳梁管旭光
Owner ZHEJIANG UNIV