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FPGA-based CRC parallel operation IP core

An operation module and matrix operation technology, which is applied in the field of data verification and can solve the problems of not supporting generator polynomials, not supporting calling CRCIP cores, etc.

Active Publication Date: 2018-02-16
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are still some defects in the IP cores provided by FPGA manufacturers. For example, Altera’s support for generator polynomials is only CRC-32, CRC-16-ANSI, and CRC-16-CCITT, which cannot support all generator polynomials. Some types of FPGA chips do not support calling the CRC IP core

Method used

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  • FPGA-based CRC parallel operation IP core
  • FPGA-based CRC parallel operation IP core
  • FPGA-based CRC parallel operation IP core

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Embodiment 1

[0089]An FPGA-based CRC parallel operation IP core, which can support all generator polynomials, can configure init, refin, refout, xorout and other parameters, and can choose 8bit, 16bit, 32bit and other common parallel processing bit widths in the industry. The circuit will be based on Different generator polynomials calculate the corresponding feature matrix, and give the corresponding CRC operation results according to different configurations of users.

[0090] The CRC parallel computing circuit proposed in this embodiment includes the following 6 modules:

[0091] 1) CRC bit width automatic identification module

[0092] The CRC bit width automatic identification module will identify the input 33-bit representation generator polynomial binary number value, and determine the bit width of the calculated CRC according to the position of the first data in the data that is 1 in the data, and the polynomial binary number The poly and the initial value init are shifted to the ...

Embodiment 2

[0139] refer to figure 1 , the IP core proposed in this embodiment contains 13 interface signals in total, including 10 input signals and 3 output signals. The meanings of the specific interface signals are as follows:

[0140] clk_in: the system clock running on the IP core, controlling all operations such as data sampling and processing;

[0141] start: The start signal for CRC to start calculation. When start is high, the data_in interface signal line will be sampled at the rising edge of the clock, and a series of operations will be performed. When start is low, sampling will stop.

[0142] mode: This embodiment includes two modes of CRC operation, one is the CRC generation mode, which is used to generate the CRC check code of the data, and the other is the CRC check mode, which is used to check whether the data is wrong, when the mode is 1 When the CRC generation mode is selected, the function of the CRC generator is realized; when the mode is 0, the CRC check mode is se...

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Abstract

The invention discloses an FPGA-based CRC parallel operation IP core. The IP core comprises a CRC bit width automatic recognition module, a refin configuration module, a feature matrix generation module, a CRC generation operation module, a CRC checking operation module and a refout / xorout configuration module, wherein the CRC bit width automatic recognition module recognizes the bit width of an input generator polynomial, the feature matrix calculation module realizes n(th)-power operation of a feature matrix by the adoption of a matrix column transformation mode, and the CRC generation operation module and the CRC checking operation module perform calculation relevant to CRC generation and CRC checking according to the obtained feature matrix, CRC bit width and parallel calculation bit width. The IP core is suitable for 8-bit, 16-bit and 32-bit CRC bit width, any generator polynomial and CRC calculation of 8-bit, 16-bit and 32-bit parallel operation bit width.

Description

technical field [0001] The invention relates to the technical field of data verification, in particular to an FPGA-based cyclic redundancy check operation IP core with configurable parameters and adjustable parallel bit width. Background technique [0002] In the communication process of data transmission, in order to detect whether the sent data has changed during the transmission process, resulting in data transmission errors, data verification technology is required. Commonly used check methods include parity check, XOR check, cyclic redundancy check (CRC check), etc., where parity check and XOR check are prone to errors in the case of multi-bit data errors. Judgment, and CRC check stands out for its advantages of simple operation and high accuracy of check results. [0003] The CRC verification realization method is divided into serial realization and parallel realization, and parallel realization is widely used at present. Parallel methods include table lookup method ...

Claims

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Application Information

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IPC IPC(8): G06F11/10
Inventor 刘洪光刘玉荣
Owner SOUTH CHINA UNIV OF TECH
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