Display device driving system and method and display device

Abstract

The invention provides a display device driving system and method and a display device. The system includes a timing controller, a flash memory chip electrically connected with the timing controller,and a burning interface electrically connected with the timing controller. The timing controller includes a read-write module, a bus switching module, and a burning detection module. Whether the burning interface is working can be detected through the burning detection module, a control signal is sent to the bus switching module according to the detection result, and the bus switching module controls whether the flash memory chip is electrically connected with either the read-write module or the burning interface according to the control signal. Therefore, the number of branches of the data bus is reduced, the time needed for burning data to the flash memory chip and the time needed for reading data from the flash memory chip are reduced, and the read-write rate of the flash memory chip isimproved.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a display device driving system and method, and a display device. Background technique [0002] With the development of display technology, liquid crystal displays (Liquid Crystal Display, LCD) and other flat display devices are widely used in mobile phones, televisions, personal Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream of display devices. [0003] A flat panel display device generally includes a display panel (Panel) and an external drive circuit, and the external drive circuit generally includes: a clock control chip (TCON) on a printed circuit board (Printed Circuit Board, PCB), a power management chip (Power manage IC) and a programmable gamma correction chip (P-gamma IC), etc., wherein the clock control chip is mainly used to convert low-voltage differentia...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, the existing flash memory chip architecture includes: a flash memory chip 100, a timing controller 200, a programming interface 300, a main serial peripheral interface (Serial Peripheral Interface, SPI) bus connecting the flash memory chip 100 and the timing controller 200 400, the branch SPI bus 500 drawn from the main SPI bus 400 and connected to the programming interface 300, during operation, the timing controller 200 reads data from the flash memory chip 100 through the main SPI bus 400 , burn data into the flash memory chip 100 through the programming interface 300 via the branch SPI bus 500, because the SPI bus of this architecture has too many branches and the wiring is too long, which increases the signal reflection, and the speed of the SPI bus is also reduced accordingly. The time for reading data from the flash memory chip, programming data to the flash memory chip, and abnormal operation of the timing controller is increased, and the work efficiency is very low

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