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LDO circuit

A circuit and circuit generation technology, applied in the field of chip power management, can solve the problems of increased circuit design complexity and power consumption, and achieve the effects of reducing design complexity, reducing area, and stable circuit operation

Inactive Publication Date: 2018-03-09
谢兴艺
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the traditional LDO circuit structure, both the bandgap reference circuit and the operational amplifier need to consume power, so there is a limit to reducing the power consumption of the traditional LDO circuit
[0005] When the chip works in a low power consumption state, the current required will be very small. If a traditional LDO circuit is used to power it in this case, the quiescent current consumed by the LDO circuit itself may be greater than the current consumed by the chip itself.
[0006] In addition, the traditional LDO circuit structure also needs to be compensated to ensure the stability of the loop, which increases the complexity of the circuit design.

Method used

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Embodiment Construction

[0013] see figure 2 As shown, the low power consumption LDO circuit described in this application includes in the following embodiments: a bias current generation circuit, a bias voltage generation circuit, and a power transistor.

[0014] The bias current generating circuit is composed of a plurality of series-connected PMOS transistors PMOSC and a first NMOS transistor MN1, wherein, among the plurality of series-connected PMOS transistors PMOSC, the gates of all PMOS transistors are grounded to GND, and the first PMOS transistor The source of the first NMOS transistor MN1 is connected to the power supply voltage VDD, the drain of the last PMOS transistor is connected to the drain and gate of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded to GND.

[0015] A plurality of PMOS transistors PMOSC connected in series are used to generate a large resistance, and the resistance combined with the first NMOS transistor MN1 can generate a bi...

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Abstract

The invention discloses an LDO circuit of a low-power-consumption linear voltage regulator. The LDO circuit comprises a power tube, a bias voltage generating circuit for providing bias voltages for the power tube, and a bias current generating circuit for providing bias currents for the bias voltage generating circuit. The power consumption and implementation complexity of the circuit can be reduced, and chip area can be reduced.

Description

technical field [0001] This application relates to the field of chip power management, in particular to a low power consumption LDO (LOW DROP-OUT linear regulator) circuit. Background technique [0002] In recent years, how to reduce the power consumption of chips has become an important issue in chip design. In the use of the chip, the chip will be in a low-power standby state in many cases. At this time, a low-power LDO circuit is needed to provide power for the chip. [0003] The traditional LDO circuit consists of a bandgap reference circuit, an operational amplifier, and resistors. Its structure is as follows: figure 1 shown. The bandgap reference circuit produces a reference voltage VREF that has nothing to do with temperature and voltage, and the feedback loop formed by the operational amplifier and power transistor MP3 is used to maintain the stability of the output voltage. [0004] In the traditional LDO circuit structure, both the bandgap reference circuit and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 谢兴艺
Owner 谢兴艺