Method, device and terminal equipment for extracting false path in gate-level netlist

Abstract

The invention discloses a method, device and terminal equipment for extracting a false path in a gate-level netlist. The extraction method includes, firstly, extracting all timing paths between clocks in different clock domains in the gate-level netlist; then, according to the termination point of the path being a sequential device, and the clock at the termination point does not contain the timing path of the starting point The filtering condition of the clock is used to sort and filter the extracted timing paths to obtain the false paths included in the gate-level netlist. Using the above method, the false paths in the gate-level netlist can be quickly extracted, so that the extracted false paths can be inspected and simulated during the SDC cleaning stage, and the shortcomings of the SOC design itself can be checked, so that SOC design problems can be found at a very early stage , greatly improving the efficiency of chip research and development.

Description

technical field [0001] The invention relates to the field of system-on-chip (SOC) design, in particular to a method, device and terminal equipment for extracting false paths in gate-level netlists. Background technique [0002] In the system-on-chip (SOC) design process, its basic flow is the process from the system description, algorithm description to the abstract level of the function description, circuit description and production process level to the concrete level. [0003] Among them, after the system description, the algorithm description level and the conversion of the algorithm into an equivalent RTL (Register Transport Level, register conversion level circuit) description through the hardware description language, the next step is to carry out the digital logic circuit written in the hardware description language. Synthesized to generate a gate-level netlist. In this step, the mapping between the synthesizable register transfer level description and the synthesis...

AI Technical Summary

Problems solved by technology

[0006] The present invention provides a method, device and terminal equipment for extracting false paths in the gate-level netlist to solve the problem of chip design caused by the shortcomings of the existing false path search methods, such as long analysis time, cumbersome search, and easy omission. The problem of extended production cycle

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