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Semiconductor device and manufacturing method thereof, and electronic device

A manufacturing method and semiconductor technology, applied to semiconductor devices, electric solid devices, circuits, etc., can solve problems such as local depth differences, line collapse, etc., to reduce local depth differences, reduce line collapse problems, and reduce local depth difference effect

Active Publication Date: 2018-03-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Aiming at the deficiencies in the prior art, the present invention proposes a new manufacturing method of semiconductor devices, which can overcome the local depth difference and line collapse problems in the manufacture of NAND flash memory STI

Method used

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  • Semiconductor device and manufacturing method thereof, and electronic device
  • Semiconductor device and manufacturing method thereof, and electronic device
  • Semiconductor device and manufacturing method thereof, and electronic device

Examples

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Embodiment 1

[0041] The following will refer to figure 2 as well as Figure 3A ~ Figure 3D A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0042] First, step 201 is performed to provide a semiconductor substrate 300 on which a patterned gate stack and an active region hard mask layer 304 are formed, the gate stack including a tunnel oxide layer 301 and floating gate 302, forming a structure such as Figure 3A shown.

[0043] Wherein, the semiconductor substrate 300 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. The layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in t...

Embodiment 2

[0069] The present invention also provides a semiconductor device fabricated by the above method, such as Figure 4 As shown, the semiconductor device includes: a semiconductor substrate 400 on which a patterned gate stack and an active region hard mask layer 404 and an isolation structure 405 separating the gate stack are formed, The gate stack includes a tunnel oxide layer 401 and a floating gate 402 .

[0070] Wherein, the semiconductor substrate 400 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. The layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the constituent material of the semiconductor substrate 400 is selecte...

Embodiment 3

[0078] Still another embodiment of the present invention provides an electronic device, including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate on which gate stacks and isolation structures for separating the gate stacks are formed.

[0079] The semiconductor substrate can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors etc. or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and / or PMOS, can be formed on the semiconductor substrate. Similarly, a conductive member may also be formed in the semiconductor substrate, and the conductive member may be the gate, source or drain...

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method includes forming an isolation structure in a semiconductor substrate, including the steps that the semiconductor substrate is provided, and a hard mask layer of the isolation structure is formed on the semiconductor substrate; the hard mask layer of the isolation structure is utilized as a mask to etch the semiconductor substrate to form a trench used for forming the isolation structure, the trench reaches a target depth through a set number of etching steps, each of the etching steps includes the following operations, the hard mask layer of the isolation structure is utilized as the mask to etch the semiconductor substrate to the set depth, and by-product obstruction operation is carried out after the etching is completed. This method is advantaged in that local depth difference and line collapse problems can be reduced. The semiconductor device and theelectronic device have reduced local depth difference and line collapse due to the above manufacturing method.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of semiconductor manufacturing technology, flash memory (flash memory) with faster access speed has been developed in terms of storage devices. Flash memory has the characteristics that information can be stored, read, and erased multiple times, and the stored information will not disappear after power failure. Therefore, flash memory has become a popular choice for personal computers and electronic devices. A widely used type of non-volatile memory. However, NAND (NAND gate) fast memory is widely used in fields with high read / write requirements due to its large storage capacity and relatively high performance. Recently, the capacity of NAND flash memory chips has reached 2GB, and the size is rapidly increasing. Solid state drives ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H10B69/00
CPCH10B41/00
Inventor 常荣耀宋洋
Owner SEMICON MFG INT (SHANGHAI) CORP