A Layout Design Method of Standard Cell Library to Reduce WPE Effect

Abstract

The present invention provides a standard cell library layout design scheme for reducing the WPE effect, which is applied in the field of semiconductor manufacturing, including the following steps, determining the basic design parameters of the standard cell layout; according to the standard cell schematic diagram and the basic design parameters , forming the basic layout of the standard cell; according to the basic layout of the standard cell, calculate the maximum distance (SC_sum) from the PMOS AA active region of the single standard cell to the N well; according to the maximum distance (SC_sum), calculate Find the optimal distance value from the source / drain terminal of the PMOS to the N well; adjust the basic layout according to the optimal distance value. Beneficial effects: the invention realizes the fixed layout and area of ​​a single standard unit, reduces the influence of the WPE effect on the standard unit, increases the threshold voltage, and increases the circuit speed by more than 5%.

Description

Technical field[0001]The present invention relates to the field of semiconductor manufacturing, and more particularly to a standard unit library layout design method for reducing WPE effects.Background technique[0002]Such asfigure 1 As shown, the well adjacent effect (WPE: Well Proximity Effect) refers to the diffusion of the atom from the edge of the mask, and the surface of the silicon wafer is dense in the vicinity of the trap, and the concentration will be in the distance mask The edges of the edge are different, resulting in uneven doping concentrations of the entire well, the threshold voltage of the MOS tube is not the same, and the circuit performance has an effect.[0003]figure 2 For a typical standard unit, a buffer, a buffer, composed of PMOS and NMOS. The disadvantage is that in the case of fixed space, the source end and the drain region of the PMOS transistor are closer to the N well distance. The source end and the drain region of the NMOS transistor are closer to the ...

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Problems solved by technology

The disadvantage is that, in the case of a fixed area, the source and drain regions of the PMOS transistor are relatively close to the N well, and the source and drain regions of the NMOS transistor are relatively close to the P sub, so PMOS and NMOS are affected by The WPE effect has a significant impact, and the threshold voltage increases, resulting in a decrease in the opening speed of the circuit, resulting in a decrease in the operating frequency of the circuit

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