Multi-time programmable (MTP) device and manufacturing method thereof

Abstract

The invention discloses a multi-time programmable (MTP) device. The MTP device comprises a first N-metal-oxide-semiconductor (NMOS) tube, a second NMOS tube and a third NMOS tube, wherein the first NMOS tube, the second NMOS tube and the third NMOS tube are used as a selection tube, a storage tube and a word line tube and are formed in a P well, a poly-silicon grid of the second NMOS tube arrangedat a middle part is a poly-silicon floating grid, a first extension end of the poly-silicon floating grid forms a programming coupling structure, a second extension end forms an erasure structure, the second extension end of the poly-silicon floating grid crosses a first active region comparing a first N well, the erasure structure also comprises a first P+ region and a first N+ region, the two injection regions are overlapped at the first active region along a direction parallel to the second extension end of the poly-silicon floating grid, the size of an overlapping region is determined according to alignment accuracy of the first N+ region and the first active region, and an effective erasure overlapping structure can be enabled to be achieved under the condition of maximum alignment deviation. The invention also discloses a manufacturing method of the MTP device. By the MTP device, the erasure efficiency of the device can be improved, and the problems of MTP erasure failure and test failure brought therefrom are prevented.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a multi-time programmable (Multi-Time Programmable, MTP) device. The invention also relates to a manufacturing method of the MTP device. Background technique [0002] like figure 1 As shown, it is a top view structure diagram of an existing MTP device; including: [0003] A P well 101, a first N well 102, and a second N well 103 formed on a semiconductor substrate such as a silicon substrate, and three NMOS transistors are formed in the P well 101, namely NMOS transistors 201, 202 and 203, 3 The three NMOS transistors have polysilicon gates 1041, 1042 and 1043 respectively, and the three NMOS transistors include four N+ regions, which are respectively N+ regions 105a, 105b, 105c and 105d, wherein the N+ regions 105b and 105c are shared by two adjacent NMOS transistors . [0004] The polysilicon gate 1042 is a floating gate, that is, a polysilicon ...

AI Technical Summary

Problems solved by technology

[0009] The existing MTP has always had the problem of insufficient process margin (margin) for the overlay of the N+ area 105e to the active area (OD), which caused insufficient erasure (Erase) efficiency, resulting in the failure of related MTP tests

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