A method of using cache as memory based on Loongson processor platform

Abstract

The invention discloses a method for using the high-speed cache of the Godson processor platform as a memory, which includes the following steps in turn: S1, ensuring the synchronization and mutual exclusion of each core of the CPU; S2, locking a shared cache with a certain capacity as the memory as required ; S3, copy the code belonging to the SEC and PEI stages of UEFI from the ROM to the shared cache used as memory in step S2; S4, set the stack and heap, jump from the assembly environment to the shared cache as C in the memory The environment continues to execute the code; S5. Execute the relevant codes of SEC and PEI and initialize the system memory; S6. After the initialization of the system memory is completed, before the execution process enters DXE from PEI, unlock the shared cache area locked by step S2 and used as memory. The method realizes using the cache memory as memory on the Loongson processor platform.

Description

technical field [0001] The invention relates to a method for using a high-speed cache as a memory, in particular to a method for using a high-speed cache as a memory based on a Godson processor platform. Background technique [0002] When the CPU starts, it usually fetches instructions from the ROM (here generally refers to ROM, EPROM, EERPOM, and NORFlash). Before the memory (RAM) is initialized to be available, the instructions to be executed by the CPU are obtained from the ROM. The XIP (eXecuteIn Place) attribute of the ROM brings certain convenience, that is, the ROM already has a part of the characteristics of the RAM, and the content on it can be read and executed directly by the CPU as instructions. However, the read-only nature of ROM and its slow reading speed also impose certain restrictions on the writing of instructions carried on it. Since the ROM is read-only, it means that the stack and heap cannot be opened for writing and updating. Therefore, instructions ...

AI Technical Summary

Problems solved by technology

The two lock mechanisms have their own advantages and disadvantages: the advantage of using the Cache15 instruction is that the virtual address can be used directly to lock the Cache operation, and if the data is not in the S-Cache, the Cache line to be locked will be retrieved to the S-Cache and then locked. The disadvantage is that the Cache lock and release operations need to be performed one by one, and there is a certain overhead; the advantage of using the lock window mechanism is that it can lock a large continuous address space by configuring it once (writing 3 lock window configuration registers). (Theoretically no more than 15 / 16 of the S-Cache capacity, that is, 3.75MB), the disadvantage is that the configuration must use physical address information, which requires special support from the operating system kernel, and there is no guarantee that the data must be in the S-Cache after configuration

[0009] The four sets of lock window registers inside the shared Cache module can be dynamically configured through the chip configuration register space, but it must be ensured that one of the 16 shared Cache channels must not be locked.