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A screening detection method for fpga configuration prom

A detection method and detection system technology, which is applied in the field of OTP type PROM screening and detection, can solve the problems of easy increase in volume, easy reduction of signal integrity in the configuration process, and easy interference in the configuration process, so as to reduce risks and reduce multiple disassembly risk, the effect of shortening the experimental cycle

Inactive Publication Date: 2020-07-17
CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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Problems solved by technology

[0003] In order to solve the problems that the existing PROM screening and detection method is easy to reduce the signal integrity of the configuration process, the configuration process is easily disturbed, and at the same time, it is easy to increase the volume and is not suitable for application in a compact load, and the like, and provides a FPGA configuration PROM Screening Assays

Method used

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  • A screening detection method for fpga configuration prom
  • A screening detection method for fpga configuration prom

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specific Embodiment approach 1

[0026] Specific implementation mode 1. Combination figure 1 with figure 2 Description of this embodiment, a screening and testing method for FPGA configuration PROM, including a screening and testing system, the screening and testing system includes a PC, a temperature-adjustable high and low temperature box, and a controller and peripheral circuits arranged in the high and low temperature box , n groups of current detection circuits, n groups of adjustable power supplies for PROMs, n groups of drivers with adjustable amplitude and level, n groups of PROMs and sockets. The controller is respectively connected with n groups of current detection circuits, n groups of adjustable power supplies of PROMs, n groups of drivers with adjustable amplitude and level, and n groups of PROMs; the controller can change the adjustable power supply of n groups of PROMs The output voltage, the amplitude and level of the output signal of n groups of drivers with adjustable amplitude and level,...

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Abstract

A method for screening and detecting an FPGA configuration PROM, relating to a method for screening and detecting an FPGA configuring a PROM, solving the problem that the existing PROM screening and detection method is easy to reduce the signal integrity of the configuration process, the configuration process is easily disturbed, and at the same time, it is easy to increase the volume and not Suitable for problems such as application in compact loads, including screening and detection systems, screening and detection systems include PCs, controllers and n groups of PROM circuits set in high and low temperature boxes; each group of PROM circuits includes current detection circuits, PROMs can be Adjust the power supply and the driver with adjustable amplitude and level; the controller is respectively connected with the current detection circuit of each group of PROM circuits, the adjustable power supply of PROM, and the driver with adjustable amplitude and level; The method of screening and testing in advance, by changing the ambient temperature, power supply voltage, control signal level and readout clock frequency, while monitoring the working current of the device, the device with poor performance is eliminated in advance, and the risk of device drop soldering is reduced.

Description

technical field [0001] The invention relates to a method for screening and detecting FPGA-configured PROMs, in particular to a method for screening and detecting OTP-type PROMs based on FPGA-configured aerospace applications. Background technique [0002] In aerospace applications, in order to improve the adaptability of the space environment, OTP (one-timeprogrammable) type PROM is usually used to store the configuration data of FPGA devices. Even if the OTP type PROM can read back the data after burning, the read data (including the first three, the last three and the accumulated sum) is the same as the original data, and the configuration may also appear when it is soldered on the circuit board that has passed the layer-by-layer inspection. If it fails, it needs to be disassembled and re-soldered. In the process of multiple disassembly, there is a risk that the entire board will be scrapped; if the PROM is soldered on a small circuit board and connected to the FPGA throug...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/267G06F11/273
CPCG06F11/267G06F11/273
Inventor 余达刘金国司国良王玉龙张艳鹏赵莹王冶
Owner CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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