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Pipelined Analog-to-Digital Converter Analog Front-End Circuit

A technology for analog front-end circuits and analog-to-digital converters, applied in analog/digital conversion, code conversion, instruments, etc., can solve problems such as large power consumption, large input signal bandwidth, and reduced circuit performance, so as to achieve low power consumption and circuit The effect of simple structure

Active Publication Date: 2021-02-26
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the prior art, due to the high clock frequency of the pipeline ADC and the large input signal bandwidth, the structure of the front-end circuit is relatively complex and the power consumption is large, which greatly reduces the performance of the entire circuit

Method used

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  • Pipelined Analog-to-Digital Converter Analog Front-End Circuit
  • Pipelined Analog-to-Digital Converter Analog Front-End Circuit
  • Pipelined Analog-to-Digital Converter Analog Front-End Circuit

Examples

Experimental program
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Embodiment 1

[0028] See figure 1 , figure 1 A schematic structural diagram of a pipelined analog-to-digital converter analog front-end circuit provided by an embodiment of the present invention. The pipelined analog-to-digital converter analog front-end circuit includes: a first Buffer unit, a second Buffer unit, a first sample and hold unit, a second sample and hold unit, a third sample and hold unit, a fourth sample and hold unit, and a clock generation unit; in,

[0029] Both the first Buffer unit and the second Buffer unit are electrically connected to the signal input terminal VIN-IN;

[0030] Both the first sample and hold unit and the third sample and hold unit are electrically connected to the first Buffer unit;

[0031] Both the second sampling and holding unit and the fourth sampling and holding unit are electrically connected to the second Buffer unit;

[0032] The clock generation unit is electrically connected to the first sample and hold unit, the second sample and hold u...

Embodiment 2

[0036] Further, on the basis of the above-mentioned embodiments, please refer to figure 2 , figure 2 A schematic structural diagram of a first Buffer unit provided by an embodiment of the present invention, the first Buffer unit includes: a first current source I D1 , the second current source I D2 , the third current source I D3 , the fourth current source I D4 , the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8; ,

[0037] The second current source I D2 . The first MOS transistor M1, the fifth MOS transistor M5, and the sixth MOS transistor M6 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND;

[0038] The first current source I D1 The second MOS transistor M2 is sequentially connected in series between the power supply terminal...

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PUM

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Abstract

The present invention relates to a pipelined analog-to-digital converter analog front-end circuit, comprising: a first Buffer unit, a second Buffer unit, a first sample and hold unit, a second sample and hold unit, a third sample and hold unit, and a fourth sample and hold unit and a clock generation unit; wherein, the first Buffer unit and the second Buffer unit are electrically connected to the signal input end; the first sampling and holding unit and the third sampling and holding unit are both electrically connected to the first Buffer unit; the second sampling and holding unit and the fourth sampling and holding unit are electrically connected to the second Buffer unit; the clock generating unit is electrically connected to the first sampling and holding unit and the second sampling and holding unit respectively , the third sample and hold unit, and the fourth sample and hold unit. The analog front-end circuit of the pipeline type analog-to-digital converter provided by the invention meets the performance requirements of the high-speed time-domain interleaving pipeline type analog-to-digital converter for the analog front-end circuit, and at the same time has a simple circuit structure and low power consumption.

Description

technical field [0001] The invention belongs to the field of analog-to-digital converters, in particular to an analog front-end circuit of a pipelined analog-to-digital converter. Background technique [0002] With the continuous development of science and technology, in many application fields, such as ultra-wideband systems, software radio systems, spectrum analyzers, electronic oscilloscopes and other communication and test systems, with the continuous increase in the bandwidth of analog input signals, the analog-to-digital conversion The performance of the device, especially the sampling rate and precision put forward higher requirements. [0003] In order to achieve a high-speed sampling rate, up to several gigahertz, time-domain interleaving technology has been favored by researchers and industries. Under the premise of realizing high sampling rate and meeting the requirement of high precision at the same time, the pipeline type analog-to-digital converter is a good c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/38H03M1/00
CPCH03M1/002H03M1/38
Inventor 朱樟明王莉莎刘马良刘术彬丁瑞雪
Owner XIDIAN UNIV