Low-power-consumption SAR ADC control logic circuit

Abstract

The invention discloses a low-power-consumption SAR ADC control logic circuit. The control logic circuit comprises a shift register module (10) and a data register module (20); the shift register module (10) comprises N improved D triggers; and the data register module (20) comprises N dynamic comparators. Compared with the traditional circuit structure, the logic unit of the data register module(20) in the invention can store comparator double-end output in an SAR ADC analog circuit at the same time by only needing a dynamic comparator; therefore, the SAR ADC control logic circuit structureis simplified; power consumption of the control logic circuit part can be effectively reduced; simultaneously, because a few transistors are adopted in the circuit structure in the invention, the chiparea is easily reduced; in addition, because positive feedback loops are increased in the dynamic comparators, the data transmission delay is reduced; and, compared with the traditional circuit, thedata transmission speed of the circuit in the invention is relatively rapid.

Description

technical field [0001] The invention belongs to the field of analog-to-digital conversion integrated circuits, in particular to a low-power SAR ADC control logic circuit. Background technique [0002] Analog to Digital Converter (Analog to Digital Convert, ADC), as a key interface circuit between analog and digital circuits, plays an important role in data processing systems. The characteristics of the successive approximation (Successive Approximation Register, SAR) ADC's small size, medium and high resolution, and low power consumption make the SAR ADC obtain a wide range of applications. In March 2014, ADI launched an 18bit SAR ADC AD7989-1, with a total power consumption of 700W at a sampling rate of 100ksps, which can be applied to battery-powered equipment, data acquisition systems, medical instruments and other fields. In recent years, with the rapid development of portable electronic terminal products and wearable devices, low-power microelectronic systems have been...

AI Technical Summary

Problems solved by technology

For the SAR ADC circuit design with more than 10 bits, the structure of the control logic circuit will become redundant and complicated, which will increase the overall power consumption of the SAR ADC circuit

[0006] 2) In the traditional control logic circuit, the positive and negative output results of the comparator need to experience the delay time of two D flip-flops from the output end of the comparator to the output end of the D flip-flop. The delay is large, which is not conducive to improving the working speed of SAR ADC

[0007] 3) For an N-bit SAR ADC circuit, at least 3N D flip-flops are required to adopt a traditional control logic circuit

Due to the use of more transistors, this will increase the area of ​​the overall circuit chip of the SAR ADC, which is not conducive to the small-sized SARADC circuit design

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