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Construction method for low-power-consumption sequential circuit

A technology of sequential circuits and construction methods, applied in the direction of reducing power consumption, logic circuits with logic functions, logic circuits, etc., can solve problems such as additional power consumption of gated circuits, improve system security and stability, and ensure correct performance, reducing system power consumption

Inactive Publication Date: 2018-05-08
王润泽
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The study of the above three basic gating circuits found that although these circuits are simple in structure, they still generate some additional power consumption, and not every flip-flop in the circuit system has redundant clocks, or some Flip-flops only have a small amount of redundant clocks in their work, so if all flip-flops are simply configured with control circuits, it may introduce unnecessary additional power consumption due to the extensive use of gating circuits

Method used

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  • Construction method for low-power-consumption sequential circuit
  • Construction method for low-power-consumption sequential circuit
  • Construction method for low-power-consumption sequential circuit

Examples

Experimental program
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Embodiment 1

[0023] A method for constructing a low-power sequential circuit. According to the state transition characteristics of the circuit system, a self-control flip-flop is constructed, and a low-power sequential circuit is constructed by using the self-control flip-flop, which eliminates redundant clock signals existing in the circuit system and reduces system power. Consumption, improve the overall performance of the circuit, specifically include the following steps:

[0024] (1) Draw the state transition diagram of the system circuit;

[0025] (2) Obtain the behavior function table of each flip-flop in the circuit from the state transition diagram;

[0026] (3) Obtain the clock signal analysis table of each flip-flop from the behavior function table;

[0027] (4) Construct a self-control trigger according to the clock signal analysis table;

[0028] (5) Construct a new circuit with a self-controlled flip-flop, test the circuit function, and give a new clock signal analysis table...

Embodiment 2

[0032] Such as figure 1 , 2 As shown, as embodiment 1 with circuit connection relationship, a new 4-bit twisted ring counter with XOR structure is provided. And compare and analyze it with the circuit in the prior art, the specific analysis is as follows:

[0033] Self-starting design in ring counter[J]. Electronic Design Engineering, 2016,24(23):177-179. A self-starting 4-bit torsion ring counter is disclosed, the circuit is as image 3 As shown, the state transition diagram can be obtained from its circuit diagram as Figure 4 As shown, the behavior function table of each flip-flop in the system can be obtained from its state transition diagram as shown in Table 1 below.

[0034]

[0035] After analyzing the clock signal effect of each flip-flop in the table, the clock signal analysis table can be obtained as shown in Table 2 below.

[0036]

[0037] Analysis of the table shows that in the 8 effective states of the twisted ring counter, there are 6 redundant clo...

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Abstract

The invention discloses a construction method for a low-power-consumption sequential circuit. For the method, according to the state transition characteristic of a circuit system, an auto-control trigger is constructed, the low-power-consumption sequential circuit is constructed by using the auto-control trigger, redundant clock signals in the circuit system are eliminated, the system power consumption is reduced and the overall performance of the circuit is improved. The method comprises the steps: drawing a state transition diagram of the system circuit; acquiring a behavioral function tableof each trigger in the circuit according to the state transition diagram; acquiring a clock signal analysis table of each trigger according to the behavioral function table; constructing the auto-control trigger according to the clock signal analysis table; and constructing a new circuit by using the auto-control trigger, testing the function of the circuit, and providing a new clock signal analysis table. For the method, the redundant clock signals maintaining 0 and 1 states can be completely suppressed, and at the same time, the clock signals of jumping Alpha jumping Beta can be effectivelyreleased, so that the redundant clock signals in the circuit system can be completely eliminated, the validity of the circuit system functions can be ensured, the system power consumption is reduced,and the system security and stability are improved.

Description

technical field [0001] The invention relates to a sequential circuit, in particular to a method for constructing a low-power sequential circuit. Background technique [0002] With the rapid development of microelectronics technology and integrated circuit technology, the integration level and working speed of the chip are constantly improving, and the power consumption of the circuit is also increasing. Excessive power consumption not only consumes a lot of power, but also causes the chip to overheat. The stability and service life of the circuit have been reduced, and the power consumption problem has become more and more prominent, which has become a major obstacle to the continued development of VLSI. The analysis of the overall power consumption of the CMOS circuit found that the clock signal is the only signal that always changes in the sequential circuit. It jumps twice in each cycle and needs to drive a large number of loads. It is the charging and discharging of the ...

Claims

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Application Information

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IPC IPC(8): H03K19/00H03K19/20
CPCH03K19/0016H03K19/20
Inventor 王润泽董坤陈宇桂林王涛陶媛勤
Owner 王润泽