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Method and system for circuit design optimization

A technology of circuit design and layout design, applied in CAD circuit design, computer aided design, calculation, etc., can solve problems such as long delay

Active Publication Date: 2021-08-31
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Placing connected elements close to each other also generally improves the performance of the circuit, since long interconnect paths are associated with excess capacitance and resistance, resulting in longer delays

Method used

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  • Method and system for circuit design optimization
  • Method and system for circuit design optimization
  • Method and system for circuit design optimization

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Experimental program
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Embodiment Construction

[0034]When routing a circuit design, it is possible to test a large number of different routings before finding a routing solution that meets the timing requirements of the design. Routing time may be extended due to non-optimal placement. In existing place and route techniques, physical synthesis optimization is performed after placement, and then the optimized design is routed. For example, physical synthesis optimizations may be performed to improve timing, noise margin, die area, and / or power usage. Physical synthesis optimization converts the physical elements of a circuit design into different (but logically identical) physical elements that meet the design requirements.

[0035] Due to changes made to the circuit design during physical synthesis optimization, the layout may no longer be optimal for the modified circuit design. Since physical composition optimization is performed after layout, layout does not take into account changes from optimization. As a result, r...

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PUM

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Abstract

In one embodiment of the invention, a processor-implemented method for placing and routing a circuit design (102) is provided. Generate the first netlist for the circuit design. Layout (108) is performed for the first netlist (106) on the target IC to produce a first layout design (110). A set of optimizations is performed (112) on the first layout design. The set of optimizations is recorded (114) in an optimization history file (116). One or more optimizations specified in the optimization history file are performed (118 / 202) on the first netlist to produce a second netlist different from the first netlist. Layout is performed (206) on the second netlist on the target IC to produce a second layout design (208) different from the first layout design. The nets of the second layout design are routed (210) to produce a placed and routed circuit design.

Description

technical field [0001] The present disclosure generally relates to placement, routing, and timing closure of resources in programmable integrated circuits. Background technique [0002] Programmable logic devices (PLDs) are integrated circuits (ICs) used to implement digital logic operations based on user-configurable inputs. Example PLDs include Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs). CPLDs typically contain multiple functional blocks based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transfers signals between functional blocks. [0003] An example FPGA includes an array of configurable logic blocks (CLBs) and rings or columns of programmable input / output blocks (IOBs). CLBs and IOBs are connected to each other through programmable interconnect structures (routing resources). CLBs, IOBs and interconnect structures are typically programmed by loading a stream...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392G06F30/398G06F30/394G06F30/34
CPCG06F30/34G06F30/392G06F30/394G06F30/398G06F2119/12G06F2119/06G06F30/347
Inventor R·阿加沃尔Z·王R·刘S·达斯
Owner XILINX INC