Power driven optimization for flash memory

Abstract

A memory device, and method of operation are disclosed. The device includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and perform the same operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin. The operations of varying energy margins are based on the required storage longevity of thedata being stored (lower energy margins for data being stored for shorter periods of time) to save energy and wear.

Description

[0001] Related Patent Applications [0002] This application claims the benefit of US Provisional Application 62 / 243,581, filed October 19, 2015, which application is incorporated herein by reference. technical field [0003] The present invention relates to non-volatile memory devices and, more particularly, to optimization of operating voltages. Background technique [0004] Non-volatile memory devices are well known in the art. For example, split gate memory cells are disclosed in US Patent 5,029,130 ​​(which is incorporated herein by reference for all purposes). The memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between a source region and a drain region. Various combinations of voltages are applied to the control gate, source, and drain to program the memory cell (by injecting electrons onto the floating gate), erase the memory cell (by removing electrons from the floatin...

AI Technical Summary

Problems solved by technology

First, the additional energy margin requires more power, which is problematic for battery-powered devices and applications

Second, overprogramming and overerasing memory cells can lead to excessive wear of those cells (i.e., nonvolatile memory degrades slightly with each program / erase cycle), which can unduly shorten the lifetime of the memory array

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