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On-chip clock circuit

A clock circuit and clock signal technology, applied in CAD circuit design, electrical digital data processing, special data processing applications, etc., can solve problems such as failure to cover faults

Active Publication Date: 2018-06-12
北京兆芯电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As the operating frequency of the chip is getting higher and higher, the traditional test method that the slow clock is provided by the automatic test machine (ATE, Automatic Test Equipment) cannot cover the faults caused by the high speed, so the full speed (at-speed) test is very important for high speed. Chips become critical

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Embodiment Construction

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0024] figure 1 It is a structural block diagram of an on-chip clock circuit 100 according to an embodiment of the present invention, as figure 1 As shown, the on-chip clock circuit 100 includes: a shift register module 101 , a pulse number module 102 , a logic module 103 , and an execution module 104 .

[0025] Wherein, the sh...

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Abstract

The invention provides an on-chip clock circuit. The on-chip clock circuit receives an enable signal to generate at least one test clock signal. The on-chip clock circuit comprises a synchronization module, a shift register module, a pulse number module, at least one logic module, and at least one execution module, wherein the enable signal is collected according to at least two clock signals to generate an enable synchronization signal, a logic signal is output according to the enable signal, a plurality of pulse numbers are generated according to the enable synchronization signal, at least one control signal is generated according to the logical signal and the multiple pulse numbers, at least one first test clock signal is generated according to the at least one control signal. The at least one first test clock signal generated by the on-chip clock circuit is synchronized with each other to ensure that both a first test mode and a second test mode can cover timing paths among different clock lines, thereby improving test coverage.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to an on-chip clock circuit supporting full-speed testing. Background technique [0002] When the chip is designed for testability (DFT, Design for Testability), the method of automatic test pattern generation (ATPG, Automatic Test Pattern Generation) is often used. The method tests different timing paths of the chip by scanning to find possible faults. [0003] As the operating frequency of the chip is getting higher and higher, the traditional test method that the slow clock is provided by the automatic test machine (ATE, Automatic Test Equipment) cannot cover the faults caused by the high speed, so the full speed (at-speed) test is very important for high speed. Chips become critical. [0004] Since the test clock required by the full-speed test is relatively high, and ATE cannot provide it, it is necessary to use the clock output by the phase-locked loop (PLL, phase-locke...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/33
Inventor 孙宝雷王鹏
Owner 北京兆芯电子科技有限公司