A System Using Latches to Transmit Signals Across Clock Domains
A cross-clock domain and signal transmission technology, which is applied in the system field of using latches to realize cross-clock domain signal transmission, can solve the lack of cross-clock domain signal transmission technology and other problems
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[0020] The system of the present invention adopts a latch (latch) with simultaneous asynchronous setting (set) and reset (reset) to realize signal cross-clock domain transmission.
[0021] see figure 1 , figure 2 And as shown in Table 1, a latch is provided in the system of the present invention, which includes a set-reset latch module (set-reset latch), and the set-reset latch module has a set terminal lat_set_b, a reset terminal lat_rst_b, output terminal q, clock signal input terminal CK; wherein, the clock signal input terminal CK inputs the clock signal aclk of the slow clock domain; the output terminal q is also used as the output terminal of the entire latch, and its output signal den_latch is sent to a The three-bit register den_pipe[2:0] composed of D flip-flops.
[0022] The latch also has a first input terminal rst1_b for active low reset, whose input is the signal cfg_reset_b triggered by a falling edge; a second input terminal set2 for active high reset, whose ...
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