I/O receiver and receiving circuit thereof
A receiving circuit and receiver technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of I/O receivers with many input ports, sharing, and large chip area, so as to ensure reliability and avoid the problem of internal structure Damage, improve the effect of antistatic ability
Active Publication Date: 2018-07-06
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0005] In the prior art, in the case of ensuring the reliability of the receiving circuit without the input voltage tolerance characteristic, it is impossible to share an input signal with the circuit with the input voltage tolerance characteristic, so that the number of input ports of the I / O receiver is still relatively large. Many, larger chip area
Method used
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[0036] figure 1 It is a schematic diagram of a circuit structure of an I / O receiver in the prior art. refer to figure 1 , the I / O receiver includes three receiving circuits, namely: a receiving circuit 11 , a receiving circuit 12 and a receiving circuit 13 . The above three receiving circuits share the same input signal, that is, the input port pad of each receiving circuit is connected to the same input port PAD of the I / O receiver. Each receiving circuit is enabled or disabled under the control of a corresponding core control signal.
[0037] For example, when the logic high level of the input signal at the PAD port of the I / O receiver is 3.3V, the kernel control signal IE_3p3v enables the receiving circuit 11, so that the level voltage V (C_3p3v) of the output signal of the receiving circuit 11 is the same as that of the input signal Level logic changes consistent. At the same time, the kernel control signal IE_1p8v disables the receiving circuit 12, and the level volta...
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The invention discloses an I / O receiver and a receiving circuit thereof. The receiving circuit comprises a protective circuit, a logic adjustment circuit and an executive circuit, wherein the protective circuit is coupled to a bias voltage input end and a power voltage input end of the receiving circuit, and is suitable to output a shielding control signal when a voltage of an input signal of an input port of the receiving circuit is a tolerant voltage and a kernel control signal is an enable control signal or a disable control signal; and the protective circuit outputs a path enable signal ora path disable signal based on the kernel control signal when the voltage of the input signal of the input port is a non tolerant voltage. In combination with the executive circuit, by applying the scheme, a receiving circuit without an input voltage tolerance characteristic and a circuit with the input voltage tolerance characteristic can share one input signal while the reliability of the receiving circuit with the input voltage tolerance characteristic is ensured.
Description
technical field [0001] The invention relates to the technical field of electronic circuits, in particular to an I / O receiver and a receiving circuit thereof. Background technique [0002] In the circuit system, communication between different chips is often required, for example, the CPU needs to exchange data with devices such as memory. In a chip, a circuit for communicating with other chips is called an input / output (Input / Output, I / O) circuit. In the I / O circuit, the circuit used to input signals to the chip is called the I / O receiver. The port through which an I / O receiver inputs an external signal is called an input port. [0003] I / O receivers usually include multiple receiving circuits, and the input signals of each receiving circuit are independent of each other. In order to support certain specific I / O protocols, reduce the number of I / O receiver input ports, and be compatible with different types of input signals, an I / O receiver in which multiple receiving cir...
Claims
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Login to View More IPC IPC(8): G06F13/38G06F13/40
CPCG06F13/385G06F13/4072
Inventor 耿彦陈捷马晓媛朱恺尚超华
Owner SEMICON MFG INT (SHANGHAI) CORP