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Method and test structure for testing bridges in adjacent semiconductor devices

A technology for testing structures and semiconductors, used in semiconductor/solid-state device testing/measurement, semiconductor device, semiconductor/solid-state device manufacturing, etc., and can solve problems such as short circuits and poor device yields

Active Publication Date: 2020-10-13
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] During semiconductor device fabrication, improper alignment of components on a semiconductor device can lead to short circuits and poor device yield

Method used

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  • Method and test structure for testing bridges in adjacent semiconductor devices
  • Method and test structure for testing bridges in adjacent semiconductor devices
  • Method and test structure for testing bridges in adjacent semiconductor devices

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Embodiment Construction

[0025] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are only examples and are not intended to limit the invention. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the required performance of the device. In addition, in the following description, forming the first member above or on the second member may include an embodiment in which the first member and the second member are formed in direct contact, and may also include an additional layer formed between the first member and the second member. The components, so that the first component and the second component may not directly contact the embodiment. For the purpose of simplicity and clarity, the various components can be drawn arbitrarily ...

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Abstract

A method of testing bridging between adjacent semiconductor devices includes forming a patterned diffusion region on a semiconductor substrate, and forming a first conductive layer over the diffusion region. The first conductive layer is patterned in the same pattern as the patterned diffusion regions. The exposed portion of the first conductive layer is removed to expose a portion of the diffusion region. A source / drain region is formed over the exposed portion of the diffusion region, and a dielectric layer is formed over the source / drain region. A third conductive layer is formed over the dielectric layer. Opposite ends of the second conductive layer are removed along the first direction to expose opposite first and second ends of the first conductive layer. A resistance is measured across the first conductive layer between the opposing first and second ends of the first conductive layer. Embodiments of the invention also relate to test structures.

Description

Technical field [0001] The embodiments of the present invention are directed to a method for testing a semiconductor device and a structure for testing. Specifically, the present invention is directed to test devices on semiconductor substrates. Background technique [0002] During semiconductor device manufacturing, incorrect alignment of components on the semiconductor device can lead to short circuits and poor device yields. Testing of the alignment of device components on a semiconductor wafer is desirable to avoid performing additional processing steps on defective devices. Summary of the invention [0003] An embodiment of the present invention provides a method for testing a bridge between adjacent semiconductor devices, including: forming a patterned diffusion area on a semiconductor substrate; forming a first conductive layer over the diffusion area, wherein , Patterning the first conductive layer into the same pattern as the patterned diffusion region; forming a second...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/34H01L29/42328H01L29/40114H10B41/00H10B41/42H10B41/30H01L22/14H01L21/311H01L21/3213H01L22/10G01R31/2812H01L22/20
Inventor 林孟汉梁佳琳谢智仁
Owner TAIWAN SEMICON MFG CO LTD