Unlock instant, AI-driven research and patent intelligence for your innovation.

Path calculation method for optical on-chip network under optical circuit switching condition

An optical-on-chip network and path calculation technology, which is applied in the field of communication, can solve problems such as inability to perceive network traffic, congestion, and delay conditions, delay, and throughput performance degradation, network communication conflicts, and congestion, etc., to improve delay performance and Improvement of communication efficiency, data transmission efficiency, improvement of communication efficiency and throughput

Active Publication Date: 2019-12-31
XIDIAN UNIV
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This path calculation method is only related to the location of the source and destination IP cores, and can only calculate a certain path for each packet. This method cannot perceive the traffic, congestion, and delay of the network, so that the path selected by the network for the packet cannot be optimal. Optimize the use of network resources, causing conflicts and congestion in network communication, and reducing delay and throughput performance
Therefore, as the number of IP cores in the chip continues to increase, the conflicts and congestions caused by inter-core communication based on optical circuit switching become very serious, and the use of dimensional order routing leads to higher communication delays and lower throughput.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Path calculation method for optical on-chip network under optical circuit switching condition
  • Path calculation method for optical on-chip network under optical circuit switching condition
  • Path calculation method for optical on-chip network under optical circuit switching condition

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] The most commonly used path selection method in the optical network on chip under the condition of the existing optical circuit switching mechanism is the dimension order path selection method. In the two-dimensional case, it includes the XY path selection method and the YX path selection method. Although the logic is simple, the existing optical Most of the path selection methods in the optical network on chip under the condition of circuit switching mechanism are based on this method. However, with the increasing data communication requirements of the optical network on chip, the dimension order path selection method of the existing optical circuit switching mechanism It has been unable to meet its network communication requirements, and provide performance such as high throughput and low delay for the network. For this reason, the present invention has launched research and innovation, and proposes an optical on-chip network path calculation method under the condition ...

Embodiment 2

[0055] The calculation method of the optical on-chip network path under the optical circuit switching condition is the same as that described in embodiment 1, step 4b) to calculate the candidate port congestion delay prediction value PC of the Pth candidate output port under the optical circuit switching condition P , the calculation formula is:

[0056]

[0057] Among them, P represents the serial number of the candidate output port, DL represents the historical value of the processing delay of the candidate output port, Indicates the number of link-building packets to be sent at the buffer of the Pth candidate output port when the link-building packet currently being served is received by the node, Indicates that the link-building packet currently being served is received by the node, and the j-th link-building packet to be sent at the buffer of the Pth candidate output port has no congestion transmission delay, and j indicates that the link-building packet currently bei...

Embodiment 3

[0061] The optical on-chip network path calculation method under the optical circuit switching condition is the same as that described in embodiment 1-2, step 4c) to calculate the candidate output port processing time delay prediction value TP of the Pth candidate output port under the optical circuit switching condition P ,Calculated as follows:

[0062]

[0063] in, Indicates the number of link-building packets to be sent at the output port cache of the Pth candidate output port in the current state, Indicates the non-congestion transmission delay of the i-th link-building packet to be sent at the output port buffer of the P-th candidate output port in the current state, PC P Indicates the predicted value of the candidate port congestion delay of the Pth candidate output port, i represents the sequence number of the link establishment packet to be sent at the output port cache of the Pth candidate output port in the current state,

[0064] In the present invention, ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an optical chip on-chip network path calculation method under the condition of optical circuit switching, which is used to solve the problems of inability to perceive network flow and delay status, high network delay and low throughput in the existing method. The implementation steps are: initialize the set of candidate output ports avail_port; determine the number of candidate ports in the set and their idle status; when both candidate ports are occupied, calculate the predicted value TP of the processing delay of the two ports 1 、TP 2 and the congestion difference rate k; select the output port according to the comparison between k and the congestion difference rate threshold value K; when only one of the two candidate ports is idle, select the idle port as the output port; when both ports are idle, select the output port according to the above One-hop transmission direction selects the output port; when there is only one port, it is designated as the output port. The invention adopts congestion prediction to make link building groups consider network traffic and congestion when selecting a path, and reduce communication loss by the number of path turns, which can be used to realize congestion perception, reduce network delay, and improve communication reliability and throughput.

Description

technical field [0001] The invention belongs to the field of communication technology, and relates to an optical on-chip network path calculation method, in particular to an optical on-chip network path calculation method under the condition of optical circuit switching, which can be used for the path selection of data transmission between IP cores on the chip, and realizes the network path calculation method based on optical circuits. High-efficiency data transmission between IP cores in a circuit-switched optical network-on-chip, while maintaining low-latency and low-loss data communication. Background technique [0002] With the increasing demand for business communication in the information field, the number of IP cores on the processor chip is also increasing. The traditional network-on-chip based on electrical interconnection can no longer meet the communication requirements of the current network-on-chip in terms of energy consumption, delay, bandwidth, and crosstalk....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04Q11/00H04L12/801H04L12/741H04L12/721H04L45/74
CPCH04L45/38H04L45/74H04L47/127H04Q11/0062H04Q2011/0073
Inventor 顾华玺朱李晶杨银堂朱樟明王琨张博文
Owner XIDIAN UNIV
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More