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SRAM memory and formation method thereof

A memory and latch technology, which is applied in the manufacture of electrical solid state devices, semiconductor devices, semiconductor/solid state devices, etc., can solve problems such as poor performance of static random access memory, improve electrical performance, improve the speed of writing data, and improve reading. The effect of write speed

Active Publication Date: 2018-08-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the performance of SRAM in the prior art is poor

Method used

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  • SRAM memory and formation method thereof
  • SRAM memory and formation method thereof
  • SRAM memory and formation method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] As mentioned in the background, the electrical performance of the SRAM memory formed in the prior art is relatively poor.

[0033] figure 1 It is a circuit diagram of a SRAM memory unit, the SRAM memory unit includes a pass transistor, a pull-up transistor and a pull-down transistor, the pass transistor includes: a first pass transistor PG1 and a second pass transistor PG2, and the pull-up transistor includes a first A pull-up transistor PU1 and a second pull-up transistor PU2. The pull-down transistor includes a first pull-down transistor PD1 and a second pull-down transistor PD2. The pull-up transistor and the pull-down transistor form a latch. For the connection relationship of the transfer transistor, pull-up transistor and pull-down transistor, refer to figure 1 .

[0034] When reading data "0", the current in PD1 must be greater than the current in PG1, otherwise the data "0" cannot be read correctly; when writing data "0", the current in PG1 must be greater tha...

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PUM

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Abstract

The present invention provides an SRAM memory and a formation method thereof. The method comprises the steps of: providing a substrate; forming a transmission transistor, wherein the method forming the transmission transistor comprises the steps of: forming a transmission gate structure on the substrate, wherein the transmission gate structure has a first side and a second side which are opposite,and a channel region is arranged in the substrate at the bottom portion of the transmission gate structure; and forming an epitaxial layer, wherein the epitaxial layer forms stress to channel regionwhich is only located in the substrate at the first side of the transmission gate structure. The method improves the electrical properties of the SRAM memory.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SRAM memory and a forming method thereof. Background technique [0002] With the continuous development of semiconductor technology, memory presents a development trend of high integration, high speed, and low power consumption. [0003] Functionally, memory is divided into random access memory (RAM, Random Access Memory) and read-only memory (ROM, Read Only Memory). When the random access memory is working, data can be read from any specified address at any time, and data can also be written to any specified storage unit at any time. The read and write operation of the random access memory is convenient and the use is flexible. [0004] Random access memory can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Among them, SRAM utilizes flip-flops with positive feedback to store data, and mainly relies on continuous power ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/283H01L21/8238H01L27/11H01L29/06H10B10/00
CPCH01L29/06H01L21/283H01L21/8238H01L2924/1437H10B10/00
Inventor 冯军宏甘正浩
Owner SEMICON MFG INT (SHANGHAI) CORP
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