SRAM memory and its forming method
A memory and latch technology, applied in semiconductor devices, electric solid-state devices, semiconductor/solid-state device manufacturing, etc., can solve problems such as poor performance of static random access memory, and achieve the effect of improving speed
Active Publication Date: 2021-09-07
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0005] However, the performance of SRAM in the prior art is poor
Method used
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[0032]As mentioned in the background, the electrical performance of the SRAM memory formed in the prior art is relatively poor.
[0033] figure 1 It is a circuit diagram of a SRAM memory unit, the SRAM memory unit includes a pass transistor, a pull-up transistor and a pull-down transistor, the pass transistor includes: a first pass transistor PG1 and a second pass transistor PG2, and the pull-up transistor includes a first A pull-up transistor PU1 and a second pull-up transistor PU2. The pull-down transistor includes a first pull-down transistor PD1 and a second pull-down transistor PD2. The pull-up transistor and the pull-down transistor form a latch. For the connection relationship of the transfer transistor, pull-up transistor and pull-down transistor, refer to figure 1 .
[0034] When reading data "0", the current in PD1 must be greater than the current in PG1, otherwise the data "0" cannot be read correctly; when writing data "0", the current in PG1 must be greater than...
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A SRAM memory and a method for forming the same, wherein the method includes: providing a substrate; forming a transfer transistor, the method for forming the transfer transistor includes: forming a transfer gate structure on the substrate, the substrate at the bottom of the transfer gate structure has a trench a channel region, the transfer gate structure has opposite first and second sides; a first epitaxial layer is formed in the substrate of the first side of the transfer gate structure, the first epitaxial layer exerts stress on the channel region, The minimum distance from the edge of the first epitaxial layer to the edge of the transfer gate structure is the first distance; a second epitaxial layer is formed in the substrate on the second side of the transfer gate structure, and the second epitaxial layer exerts stress on the channel region , the material of the second epitaxial layer is the same as that of the first epitaxial layer, and the minimum distance from the edge of the second epitaxial layer to the edge of the transfer gate structure is a second distance, and the second distance is greater than the first distance. The method can improve the electrical performance of the SRAM memory.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SRAM memory and a forming method thereof. Background technique [0002] With the continuous development of semiconductor technology, memory presents a development trend of high integration, high speed, and low power consumption. [0003] Functionally, memory is divided into random access memory (RAM, Random Access Memory) and read-only memory (ROM, Read Only Memory). When the random access memory is working, data can be read from any specified address at any time, and data can also be written to any specified storage unit at any time. The read and write operation of the random access memory is convenient and the use is flexible. [0004] Random access memory can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Among them, SRAM utilizes flip-flops with positive feedback to store data, and mainly relies on continuous power ...
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IPC IPC(8): H01L21/8244H01L27/11
CPCH10B10/12
Inventor 甘正浩冯军宏
Owner SEMICON MFG INT (SHANGHAI) CORP