Random access memory and preparation method thereof

Abstract

The invention provides a random access memory and a preparation method thereof. The random access memory comprises an integrated module arranged on an insulation bottom layer. The integrated module comprises a first conductor layer, a three-dimensional CMOS unit layer, a memory unit layer and a second conductor layer, which are stacked up and connected in sequence. The three-dimensional CMOS unitlayer comprises one or more three-dimensional CMOS units. The three-dimensional CMOS unit layer also comprises a grid electrode layer having at least one through hole; and at least one active region,which passes through the through hole in a one-to-one correspondence manner and is connected with the grid electrode layer, the memory unit layer and the first conductor layer. The active region comprises a source region and a drain region. The source region and the drain region are arranged at the two sides of the grid electrode layer respectively. Compared with a plane CMOS unit, the source anddrain electrodes of which are arranged at the left and right sides of the grid electrode, in the prior art, for a memory that requires the CMOS to provide an effective drive current to supply to the memory unit, the device with the same channel width reduces plane area of the CMOS unit, thereby improving storage density of the random access memory.

Description

technical field [0001] The present invention relates to the technical field of memory, in particular to a random access memory and a preparation method thereof. Background technique [0002] At present, in order to increase the density of random access memory (RAM) such as STT MRAM, the method of reducing the planar area of ​​the storage unit is usually used. However, in order to reduce the planar area of ​​the storage unit, the process node needs to be continuously improved, which poses challenges to the cost and process. [0003] Moreover, the existing random access memory usually consists of a MOS transistor, a storage unit and several connection lines. The MOS transistor plays the role of address selection. The drain of the MOS transistor is connected to one end of the storage unit. When the gate is turned on, the source, The drain, the storage unit and the bit line form a loop, and when the random access memory is an STT MRAM, the storage unit is a magnetic tunnel junct...

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present invention is to provide a random access memory and its preparation method, to solve the problem in the prior art that the density of memory cells in the random access memory is limited by the area of ​​the mounted CMOS tube

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