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Array substrate and preparation method thereof, display panel and display device

An array substrate and via hole technology, applied in semiconductor/solid-state device manufacturing, organic semiconductor devices, optics, etc., can solve problems such as hole depth, poor process, and etching film thickness

Active Publication Date: 2018-08-31
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0012] However, due to the need to etch through the interlayer insulating layer 16 and the buffer layer 12 at the same time, the etched film layer is thicker and the hole is deeper, which is prone to process defects, such as lap breaks

Method used

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  • Array substrate and preparation method thereof, display panel and display device
  • Array substrate and preparation method thereof, display panel and display device
  • Array substrate and preparation method thereof, display panel and display device

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Embodiment Construction

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0059] An embodiment of the present invention provides a method for preparing an array substrate, such as figure 2 shown, including the following steps:

[0060] S20, as shown in FIG. 3(a) and FIG. 3(b), on the substrate 10, a light-shielding layer 11 of metal conductive material and a gate line 19 are formed through a patterning process.

[0061] S21, as shown in FIG. 4(a), FIG. 4(b) and FIG. 4(c), on the substrate 10 formed with the light-shielding layer 1...

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Abstract

Embodiments of the invention provide an array substrate and a preparation method thereof, a display panel and a display device which relate to the technical field of display; and the defect rate in amanufacture process of the array substrate is reduced. The preparation method of the array substrate includes the following steps of: forming a light shield layer and a grid line of metal conductive materials on a supporting base by one-time composition process; forming a buffer layer through the one-time composition process, wherein the buffer layer includes a first via hole exposing the grid line and a second via hole exposing the light shield layer; forming an oxide active layer and a gate insulation layer through the one-time composition process; and forming a first electrode layer throughthe one-time composition process, wherein the first electrode layer includes a grid electrode, a source electrode, a drain electrode, a data line and a first connection electrode. The first connection electrode is in insulation with the grid electrode, the source electrode, the drain electrode and the data line; the first connection electrode is in electric connection with the grid line through the first via hole; the source electrode and the drain electrode are in direct contact with the oxide active layer; and the source electrode is in electric connection with the light shield layer through the second via hole.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background technique [0002] Compared with the conventional back channel etch (BCE) and etch stop (ESL) thin film transistors, the top gate structure type oxide thin film transistor has the following advantages: it significantly reduces the parasitic capacitance, which is more conducive to the realization of good driving Effect; it can reduce the production size, which is more conducive to the realization of high-resolution display requirements; it can reduce the thickness of the gate insulating layer, which is conducive to further reducing the overall production thickness; it can achieve more stable electrical characteristics of thin film transistors, thereby Improve the reliability of the display panel. [0003] However, there are still many restrictions on the design and proce...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/77H01L27/12
CPCH01L27/1214H01L21/77H10K71/00H10K71/231H01L29/78633H01L29/7869H01L29/66969H10K59/126G02F1/136209G02F1/1368G02F2201/123H01L27/1218H01L27/1225H01L27/1248H01L27/1288G02F1/13685H10K59/131H10K59/1201H10K2102/103
Inventor 刘威
Owner BOE TECH GRP CO LTD
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