FPGA implementation method and apparatus of universal quasi-cyclic LDPC code encoder

Abstract

The invention discloses an FPGA implementation method and apparatus of a universal quasi-cyclic LDPC code encoder. According to the method disclosed by the invention, compromised quantitative calculation is performed according to the requirements of the number of cyclic blocks of a non-unit matrix portion of a generated matrix, the dimensionality of the cyclic block, a code length, a code rate, asystem clock and an encoding rate, so as to figure out the parallelism of a part of parallel encoding modules. The method not only has computational and configuration versatility, but also achieves good compromise between the coding rate and the number of consumed resources, thereby overcoming the problems that the encoding rate of a serial input encoder is too low, too many resources are consumedby a fully parallel input encoding circuit, it is not conducive to the reasonable use of the resources, and that the logic connection of a two-step encoding circuit is complicated.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a general-purpose FPGA implementation method and device for a quasi-cyclic LDPC code encoder. Background technique [0002] Among various current channel coding schemes, low-density parity check codes (LDPC) are one of the most promising channel coding schemes that are closest to the Shannon limit. The LDPC code was proposed by Gallager in 1962, but it did not receive much attention in the next 35 years. Until 1981, Tanner represented the LDPC code with a graph, which was called the Tanner graph. In the 1890s, LDPC codes were finally rediscovered by Mackay, Luby and other scholars, and they did related research. Mackay expressed the parity check matrix of LDPC codes with Tanner graph, and found that LDPC codes based on belief propagation iterative decoding (BP) is a kind of channel coding whose performance is close to the Shannon limit, and its decoding complexit...

AI Technical Summary

Problems solved by technology

The hardware implementation complexity of the serial input encoding circuit is proportional to the number of check bits, and the consumption of the encoding clock is proportional to the number of information bits, so it is difficult to handle the situation of high information rate.

The parallel input encoding circuit consumes much more hardware resources such as registers than the serial input encoding circuit, which is not conducive to the rational use of resources

Two-stage encoding circuit, which consumes more flip-flop resources and less logic resources, but the logic connection is complicated

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