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Symbol LMS algorithm and system for assembly line ADC calibration

An LMS algorithm and pipeline technology, applied in the direction of analog/digital conversion calibration/test, electrical components, code conversion, etc., can solve the problem of failing to reach convergence speed and misalignment accuracy, increasing misalignment accuracy, and unable to reduce convergence speed and misalignment accuracy And other issues

Inactive Publication Date: 2018-09-28
CHONGQING UNIV OF POSTS & TELECOMM
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AI Technical Summary

Problems solved by technology

The traditional LMS (least mean square algorithm) algorithm used for pipeline ADC calibration uses a fixed step size to update the tap weight coefficient, which cannot reduce the contradiction between its convergence speed and offset accuracy
Part of the variable step size algorithm only slightly improves the convergence speed, but the misalignment accuracy will also increase, but it cannot achieve both convergence speed and misalignment accuracy

Method used

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  • Symbol LMS algorithm and system for assembly line ADC calibration
  • Symbol LMS algorithm and system for assembly line ADC calibration
  • Symbol LMS algorithm and system for assembly line ADC calibration

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Embodiment Construction

[0033] The technical solutions in the embodiments of the present invention will be described clearly and in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the invention.

[0034] The technical scheme that the present invention solves the problems of the technologies described above is:

[0035] The application example of the present invention adopts a 12bit 100MS / s pipeline ADC. The calibration work platform adopts Virtex-5ML507 (XC5VFX70T), which is a high-performance FPGA based on 65nm process.

[0036] figure 1Shown is the comparison diagram of the error convergence curve of the present invention, and the FSS in the figure is the output curve diagram of the traditional LMS. Here it refers to the analysis of the output error after calibration using the progressive mode and the oscillation mode respectively. The FSS algorithm adopts a gradual mode during calibration, an...

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Abstract

The present invention claims a symbol variable step size LMS algorithm (SVSS-LMS) and system. By judging the positive or negative deviation of an input transient error, a positive fixed constant valueis incremented or decremented for modification each time for step size iteration. The method and the system have the advantages of high calibration accuracy and fast convergence speed. Based on the traditional LMS algorithm, a symbol function sign is introduced to update a step factor mu(n) so as to achieve step size control. The size of the step factor mu(n) can be dynamically adjusted accordingto the speed of error convergence; therefore, the weight is updated faster by the error; the updated weight is fed back to an adaptive filter to improve the accuracy of the assembly line ADC output,so that the output of the assembly line to be calibrated gradually approaches the output of the low-speed but high-precision ADC.

Description

technical field [0001] The invention belongs to digital signal processing and digital integrated circuit design. Especially related to algorithm research and FPGA hardware structure design in digital signal processing. Background technique [0002] The analog-to-digital converter (ADC) is the front end of the digital signal processing system, and its performance directly affects the performance of the entire system. With the continuous improvement of digital signal processing capabilities, the requirements for digital output performance indicators of ADC devices serving as a bridge between analog systems and digital systems will become higher and higher. [0003] With the advancement of integrated circuit technology, the performance of ADC devices has been greatly improved. Under the conditions of the existing nanoscale integrated circuit manufacturing process, due to the precise control of the process equipment, the process error problems such as the mismatch of the CMOS ...

Claims

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Application Information

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IPC IPC(8): H03M1/10
CPCH03M1/1014
Inventor 王巍杨皓李双巧黄孟佳何雍春袁军
Owner CHONGQING UNIV OF POSTS & TELECOMM
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