Analog decision feedback equalization circuit for high-speed SerDes

Abstract

The invention provides an analog decision feedback equalization (DFE) circuit for a high-speed SerDes, which comprises a delay unit, a multiplier and a coefficient update circuit, wherein the coefficient update circuit generates a coefficient by means of a symbolic LMS algorithm. The analog decision feedback equalization circuit is characterized in that the delay unit and the multiplier are an analog delay unit and an analog multiplier respectively, and the delay of a signal is realized through the analog delay unit; the multiplication of the coefficient and an output signal of the analog delay unit is realized through the analog multiplier; and the output of the analog multiplier is realized through current summing. The analog DFE circuit for the high-speed SerDes realizes functions of the DFE circuit through the analog multiplier and the analog delay unit, improves the highest rate and speed capable of being supported by the circuit and can reduce the area at the same time.

Description

technical field [0001] The invention belongs to the design technology for electronic circuits, and relates to an analog DFE circuit and method for high-speed SerDes. Background technique [0002] In high-speed SerDes circuits, as the data rate continues to increase, the impact of the channel on data transmission is becoming more and more serious. The intersymbol interference phenomenon will cause problems in the judgment of the signal at the data receiving end. Therefore, a DFE circuit is required to process the signal. . In common applications, the DFE circuit implements multiplication and delay operations through a digital multiplier and a DFF circuit. With the continuous improvement of data transmission rate, the speed of digital DFF is limited; the area of ​​digital multiplier circuit is large and the speed is limited, which limits the further increase of SerDes circuit rate. Contents of the invention [0003] The purpose of the present invention is to propose an ana...

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Problems solved by technology

[0004] In order to solve the problem of insufficient speed and large area of ​​the existing high-speed SerDes circuit multiplier, the present invention provides an analog DFE circuit for high-speed SerDes, which realizes coefficients and input signals in the DFE circuit through an analog multiplier Multiplication; the circuit uses an analog delay unit to achieve signal delay; the output digital signal of the LMS algorithm is used as a switch to control the current of the multiplier, and the coefficient in the DFE circuit is changed by changing the current; the output of different DFE Taps is realized by summing the current

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