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Apparatus and method for network tracking previous level subtraction

A layered and networked technology, applied to devices and fields where the network tracks previous layered subtractions, and can solve problems such as ambiguity

Active Publication Date: 2021-11-12
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem is that when an open or short is detected, it is not clear whether the open or short is at the current via level or at the previous level of the structure

Method used

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  • Apparatus and method for network tracking previous level subtraction
  • Apparatus and method for network tracking previous level subtraction
  • Apparatus and method for network tracking previous level subtraction

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Embodiment Construction

[0019] In accordance with the methods herein, during a chip defect inspection will be separate from the current level to the previous level defects. Notably, the electron beam voltage contrast inspection throughput (throughput) is very limited. The current tools are only available to check tens of thousands of hotspots on the wafer per hour, and over the number of holes on the wafer is billions of dollars. Therefore, knowing where to check the success of the promotion examination. Previous level of random checks do not apply to the previous level deduction can not be used. By identifying vias due to open or short circuit easily via systematic failures and location of the through hole to perform a connectivity check list limit position, according to the process described herein to determine where the inspection in the inspection level.

[0020] Communication test means a state electrically connected to the measurement chip, to verify normal connections with other circuit means. Thi...

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Abstract

The invention relates to a device and method for network tracking previous layer subtraction, and discloses a method for performing a connectivity test of an integrated circuit structure in a chip. The connectivity test is performed at the first level of the chip. Potential defect locations are identified in the chip, which represent via locations that are susceptible to systematic failure due to via opens or via shorts. The potential defect locations are converted to second-level via locations of the chip. The second level is located below the first level. After switching hotspots, the second level is checked for defects. Check the via location on the first level for defects. All defects of the second level are converted to the via locations of the first level. A network trace of a defect is formed using the conversion defect of the second level and the prior level subtraction of the defect of the first level.

Description

Technical field [0001] The present invention relates to a semiconductor integrated circuit device manufacturing, in particular, it relates to methods such as an integrated circuit inspection and defect detection. Background technique [0002] Due to continuous technological innovation in the field of semiconductor manufacturing, we are developing a larger scale integration and higher density of devices, and lower power consumption and higher operating speed of the integrated circuit chip. In general, for the manufacture of integrated circuits, using a front-end process (front-end-of-line; FEOL) process discrete semiconductor device is formed in the surface of the silicon wafer technology, followed by performing back-end processing (back-end-of- line; BEOL) process circuit techniques to form a multi-level metal interconnection network over the semiconductor device, thereby providing a contact between the wires and to form desired semiconductor device. When the semiconductor integr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/20G01R31/2853G01R31/307H01L22/12H01L22/14
Inventor O·D·帕特森P·林高维鸿
Owner GLOBALFOUNDRIES U S INC MALTA