Batch memory scheduling method based on Bank division

Abstract

The invention discloses a batch memory scheduling method based on Bank division. According to the method, first, according to sources of memory requests, the memory requests are divided into CPU memory requests and GPU memory requests, and the CPU memory requests and the GPU memory requests are synthesized into batch buffer requests respectively; and second, batch memory requests needing to be processed are selected from a CPU batch buffer and a GPU batch buffer, wherein if the batch GPU memory requests are selected, the memory requests to be processed next time are selected by use of the scheduling strategy of first-ready first-come-first-serve (FR-FCFS) of row buffer hitting priorities; and if the batch CPU memory requests are selected, a Bank needs to be divided, so that memory access requests of different kernels are mapped to different Banks, and the memory access requests of multiple CPU applications are isolated. Through the technical scheme, mutual interference of multiple CPUmemory access requests and multiple GPU memory access requests is eliminated, the characteristics of the memory access request of each kernel are reserved to the maximum extent, the hit rate is increased, and therefore the purposes of lowering memory power consumption and improving system performance are achieved.

Description

technical field [0001] The invention belongs to the field of computer system memory system structure, and in particular relates to a high-performance-oriented batch memory scheduling method based on Bank division. Background technique [0002] Heterogeneous multi-core architecture, which integrates multiple CPUs and GPUs on the same chip, has gradually become the mainstream as an advanced architecture. Modern memory systems mainly reduce power consumption and improve performance based on the principle of locality of memory access requests. The CPU and GPU under the heterogeneous multi-core architecture share the on-chip main memory, so memory requests from different cores will compete for shared memory resources and interact with each other. Interference, the locality of memory access requests of individual applications gradually disappears, which seriously affects the overall system performance. The interference of memory requests is mainly divided into two types, the inte...

AI Technical Summary

Problems solved by technology

There is also interference between memory requests from multiple CPU applications. Each core hopes that its own memory access requests can be processed quickly. This competition destroys the characteristics of a single program memory access request, making the memory access request random. Enhanced performance, unable to take advantage of the locality principle of memory access requests, greatly reducing the hit rate of memory access

The reduction of the hit rate not only increases the power consumption of the system, increases the access delay, but also exacerbates the memory wall problem

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