A low-latency viterbi decoding method and system
A decoding system and low-latency technology, applied in the field of data communication, can solve problems such as unacceptable delay, and achieve the effects of improving response speed, reducing delay, and wide applicability
Active Publication Date: 2022-04-29
广东华芯微特集成电路有限公司 +1
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Therefore, for some applications with high real-time requirements, the delay of this method is unacceptable
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[0029] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. It is only stated here that the words for directions such as up, down, left, right, front, back, inside, and outside that appear or will appear in the text of the present invention are only based on the accompanying drawings of the present invention, and are not specific to the present invention. limited.
[0030] see figure 1 , figure 1 Show the flowchart of the low-latency Viterbi decoding method of the present invention, including:
[0031] S1, the branch metric calculation unit calculates each branch metric corresponding to the convolutional code;
[0032] S2, the addition, comparison and selection unit adds each branch metric to the corresponding cumulative metric to obtain each current metric, takes the path corresponding to the current metric with a smalle...
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The invention discloses a low-latency Viterbi decoding method, comprising: S1, a branch metric calculation unit calculates each branch metric corresponding to a convolutional code; S2, an addition and selection unit adds each branch metric to a corresponding cumulative metric Each current metric is obtained, and the path corresponding to the current metric with a smaller value is used as the surviving path, and the current metric corresponding to the surviving path is used as a new cumulative metric; S3, the surviving path calculation unit calculates the survival path in each cycle in real time For the path, after the constraint length of the preset multiple, the highest bit data of all surviving paths converges to the same decoded value, and the decoded value is output and the remaining data of the surviving paths are sequentially shifted to the left. The invention also discloses a low-delay Viterbi decoding system. By adopting the present invention, the delay can be reduced to 5 times the constraint length through the method of updating the surviving path in real time, thereby effectively reducing the delay required by the commonly used backtracking method and improving the response speed of the system.
Description
technical field [0001] The invention relates to the technical field of data communication, in particular to a low-delay Viterbi decoding method and a low-delay Viterbi decoding system. Background technique [0002] In data communication, the Viterbi decoding algorithm is a commonly used maximum likelihood algorithm. By finding the maximum likelihood state transition path on the trellis diagram, the error correction decoding of the received signal is realized. [0003] A common Viterbi decoder usually includes the following three parts: [0004] A branch metric calculation unit (Branch Metric Unit, BMU), configured to calculate the metric corresponding to each branch of the received convolutional code. [0005] Add compare select unit (Add Compare Select, ACS), used to add the branch metric and the cumulative metric, and select the path with the smaller sum as the surviving path, and use this sum as the new cumulative metric. [0006] The Traceback Judgment Unit (Traceback ...
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IPC IPC(8): H03M13/41H04L1/00
CPCH03M13/41H04L1/0054
Inventor 陈雪松
Owner 广东华芯微特集成电路有限公司