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Chip Packaging Method

A chip packaging and chip technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of single wafer large fragmentation risk, wafer fragmentation, expensive equipment costs, etc., to avoid wafer fragmentation problems and improve product quality. Yield rate and packaging cost reduction effect

Active Publication Date: 2021-02-12
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to many unstable factors during separation, there will be a great risk of fragmentation during the separation of a single wafer from the carrier
For example, when thermal sliding is used for debonding, the separated thin wafers are prone to warpage and fragmentation risk at high temperature; if the mechanical debonding method based on Zonebond technology is used, the bonded body needs to be pre-soaked before debonding. For a long time, there is mechanical stress on the surface that causes debonding, which can easily cause wafer fragments
In addition, the equipment cost of the latter debonding method is more expensive

Method used

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Examples

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Embodiment

[0053] The embodiment of the present invention provides a chip packaging method, such as figure 1 shown, including the following steps:

[0054] Step S11, bonding the wafer 1 to be packaged with the carrier 2 (see Figure 4 ), wherein, there are several grooves 21 in the carrier 2, and the grooves 21 and the wafer 1 form an accommodating cavity.

[0055] In this embodiment, the wafer 1 to be packaged is a silicon chip, the carrier 2 is preferably a bare silicon chip with a thickness of 200 microns, and the periphery of the groove 21 on the carrier 2 is a support portion 22 . The bonding of wafer 1 and carrier 2 is actually the bonding of wafer 1 and the supporting part 22 on carrier 2. Generally, temporary bonding or permanent bonding can be selected. Temporary bonding can use temporary bonding glue, permanent bonding Screen printing can be selected, and the bonding material is selected from one of glue, metal, glass paste, and the like. In this embodiment, a permanent bond...

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Abstract

The invention relates to the technical field of chip packaging and particularly discloses a chip packaging method. The chip packaging method comprises the following steps of bonding a to-be-packaged wafer and a slide, wherein a plurality of grooves are formed in the slide and an accommodating cavity is formed by the grooves and the wafer; thinning the wafer; and cutting the thinned wafer along support parts on the peripheries of various grooves to obtain a plurality of chips, wherein the cutting width is greater than or equal to the widths of the support parts. The slide is bonded to the to-be-packaged wafer through the support parts on the slide, the cutting width is greater than or equal to the widths of the support parts during subsequent cutting, that is to say, the slide and the support parts can be cut off together during cutting, and a de-bonding process is omitted, so that the problem of a wafer fragment during de-bonding in the prior art can be avoided and the product yield isimproved. Furthermore, according to the chip packaging method, a de-bonding device does not need to be used, so that the packaging cost is greatly reduced.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip packaging method. Background technique [0002] In recent years, as semiconductor devices continue to respond to the demand for "faster, cheaper, and smaller", three-dimensional stacking 3D integration technology has entered mainstream semiconductor manufacturing. Among them, TSV (Through Silicon Via) technology is interconnected through vertical chip vias, which brings shorter interconnection length and smaller packaging area, greatly improves signal transmission speed and reduces parasitic power consumption. In order to meet the requirements of TSV manufacturing, thinning wafers is the general trend. But ultra-thin device wafers are flexible and fragile, prone to warping and undulation, so a support system is needed to make TSV processing go smoothly. In this context, temporary bonding and debonding technology came into being. [0003] The existing three-dimens...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/78H01L21/56
CPCH01L21/561H01L21/568H01L21/78H01L2224/14181
Inventor 任玉龙
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD
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