Chip Packaging Method
A chip packaging and chip technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of single wafer large fragmentation risk, wafer fragmentation, expensive equipment costs, etc., to avoid wafer fragmentation problems and improve product quality. Yield rate and packaging cost reduction effect
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[0053] The embodiment of the present invention provides a chip packaging method, such as figure 1 shown, including the following steps:
[0054] Step S11, bonding the wafer 1 to be packaged with the carrier 2 (see Figure 4 ), wherein, there are several grooves 21 in the carrier 2, and the grooves 21 and the wafer 1 form an accommodating cavity.
[0055] In this embodiment, the wafer 1 to be packaged is a silicon chip, the carrier 2 is preferably a bare silicon chip with a thickness of 200 microns, and the periphery of the groove 21 on the carrier 2 is a support portion 22 . The bonding of wafer 1 and carrier 2 is actually the bonding of wafer 1 and the supporting part 22 on carrier 2. Generally, temporary bonding or permanent bonding can be selected. Temporary bonding can use temporary bonding glue, permanent bonding Screen printing can be selected, and the bonding material is selected from one of glue, metal, glass paste, and the like. In this embodiment, a permanent bond...
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