Non-uniform bus (NUB) interconnect protocol for tiled last level caches

Abstract

Provided are a method and an apparatus for non-uniform bus (nub) interconnect protocol for tiled last level caches. The apparatus includes a plurality of central processing units, a plurality of coreinput / output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 505,313, filed May 12, 2017, with the USPTO and U.S. Patent Application No. 15 / 677,739, filed August 15, 2017, with the U.S. Patent and Trademark Office , the entire contents of these applications are hereby incorporated by reference. technical field [0002] The present disclosure relates generally to cache memories, and more particularly, to a method and apparatus for a non-uniform bus interconnect protocol for tiled last level caches. Background technique [0003] The last level cache (LLC) in a central processing unit (CPU) is typically sized to hold several megabytes of recently memory accessed data or instruction line to reduce the latency of requests from the CPU. A cache memory storing several megabytes of data requires a large physical area and integrated circuit board to plan resources to provide maximum capacity with minimum response delay. In a multi-CPU multi-LLC bank shared ...

AI Technical Summary

Problems solved by technology

In a multi-CPU multi-LLC bank shared cache system, an interconnect network (sometimes referred to as a network-on-chip (NoC)) provides high bandwidth between the main CPU and the LLC bank, but each An instantiation that scales wire, power, time and area requirements exponentially

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