26 results about "Interconnect agreement" patented technology

A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.

The present application relates to the technical field of data storage, and specifically discloses a data transmission method and device, a heterogeneous system, and a coherent interconnect processing component. The coherent interconnect processing component installed on a device enables corresponding coherent interconnect interfaces on the basis of the number of other devices to be interconnected in a heterogeneous system where said device is located, initializes physical communication links to obtain memory interconnect parameters, establishes memory coherent interconnect communication links between the devices on the basis of the memory interconnect parameters, allocates corresponding cache spaces from said device, and on the basis of the memory coherent interconnect communication links and the cache spaces, performs cache coherent transaction processing of said device and the other devices, so as to implement memory coherent interconnect transmission requests between said device and the other devices. Therefore, topologies can be dynamically sensed, and memory coherent interconnect communication links between devices in a heterogeneous system can be automatically established, thereby mitigating the problem that different device interconnect protocols need to be managed in the heterogeneous system, achieving inter-device cache coherence, and further improving the access performance.

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

The invention relates to the technical field of chip design, in particular to a high-speed interconnection interface system, which comprises an on-chip interface relay module supporting bidirectional data transmission, an interconnection protocol conversion module and a physical layer processing module, and is characterized in that the on-chip interface relay module is configured to receive an instruction and generate a transaction signal conforming to an on-chip interface protocol specification; the interconnection protocol conversion module is configured to receive a transaction signal, obtain user-defined information, insert the user-defined information into a user field of the transaction signal and package the user-defined information into a data frame conforming to a user-defined transmission protocol specification of the physical layer processing module; wherein the user-defined information carries an address field segment of a physical transmission channel; the physical layer processing module comprises N independent physical transmission channels, wherein N is greater than or equal to 1; each physical transmission channel comprises a sending end, and the sending end is configured to receive the data frame, process the data frame and then send the data frame, so that the purposes of supporting N physical transmission channels and customizing a transmission protocol are achieved.

The invention relates to tunneling of peripheral bus protocol traffic over a consistent fabric and an inter-chip or inter-die bus. A peripheral device includes: a master chip, the master chip including a coherent interconnect; one or more first peripheral bus modules; an inter-chip (C2C) or inter-die (D2D) interface; and one or more tunnel adapters. A coherency interconnect is used to connect electronic components of a peripheral device according to a coherency interconnect protocol. The one or more first peripheral bus modules are configured to communicate according to a peripheral bus protocol. The C2C or D2D interface is to communicate with an auxiliary chip comprising one or more second peripheral bus modules over a C2C or D2D bus. The one or more tunnel adapters are configured to transmit peripheral bus packets of a peripheral bus protocol between the first and second peripheral bus modules over the coherency interconnect and the C2C or D2D bus by transitioning between the peripheral bus packets, messages of the coherency interconnect protocol, and C2C or D2D bus messages.

A control method for error handling in a controller, a storage medium thereof, the controller, and a storage device. The controller is used in a first device capable of linking a second device in accordance with an interconnection protocol. The control method includes the steps of: processing, by the controller, first error information by sending a negative acknowledgement control message to the second device in accordance with the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performs data reception at a protocol layer in accordance with the interconnection protocol; and setting error handling state data to indicate that error handling is declared for the first error information, so that the controller does not handle a sequence number error that occurs after the first error until the error handling state data is set to indicate that the error handling is undecleared.

Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

The present application relates to the field of communication technology, and provides a network connection method and related products, the method comprising: obtaining the registration status of an Internet Multimedia Subsystem (IMS) network; obtaining the bearer establishment status; if the registration status of the IMS network is unsuccessful registration, and the bearer establishment status is successful bearer establishment, instructing a modem to restart to connect to the IMS network. The above method can restore call services without user perception, thereby improving user experience.

A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.

A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.

Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC / ECC combinations can be used based on the interconnect protocol and the link operational conditions.

In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.

The present application provides a network activation method, device, equipment and storage medium. The method includes: obtaining a circuit activation request, the circuit activation request is used to request the activation of an Internet dedicated circuit; determining network resources according to the circuit activation request, the network resources including a target device, a physical port number, an IP Internet Protocol address, a VLAN virtual local area network number and an IP Internet Protocol gateway number; verifying and processing the network resources to obtain a resource status of the network resources, the resource status being an available state or an unavailable state; when the resource status is an available state, generating configuration parameters of the target device, and sending the configuration parameters to the target device. The method of the present application solves the problem of low efficiency and low accuracy of service activation in the traditional activation method.

The present disclosure relates to the technical field of data transmission, and specifically to a data transmission method and device, and a data transmission system, wherein the method comprises: establishing a communication connection between a terminal device and a redirection server; the redirection server obtains the Internet Protocol address of the terminal device, and determines the network type corresponding to the Internet Protocol address; the redirection server determines a target server among multiple data servers according to an allocation strategy, and determines the server identifier of the target server according to the network type, and sends it to the terminal device; the terminal device receives the server identifier, and connects to the target server according to the server identifier. The technical solution of the embodiment of the present disclosure improves the convenience of establishing a connection between a terminal device and a data server and the reliability of data transmission in the prior art.

Method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. The method is suitable for an electronic device capable of communicating with another electronic device. The method comprises the following steps. At a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b / 10b encoding. At the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. The test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.

The present invention relates to the field of chip design technology, and in particular to a high-speed interconnection interface system, which includes an on-chip interface relay module supporting bidirectional data transmission, an interconnection protocol conversion module and a physical layer processing module, wherein the on-chip interface relay module is configured to receive instructions and generate transaction signals that comply with the on-chip interface protocol specification; the interconnection protocol conversion module is configured to receive the transaction signal and obtain user-defined information, insert the user-defined information into the user field of the transaction signal and encapsulate it into a data frame that complies with the custom transmission protocol specification of the physical layer processing module; wherein the user-defined information carries the address field of the physical transmission channel; the physical layer processing module includes N independent physical transmission channels, wherein N≥1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to receive a data frame, process it, and then transmit it, thereby achieving the purpose of supporting N physical transmission channels and custom transmission protocols.

The invention relates to the technical field of network security, and provides a content distribution network back-to-source method and device, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a candidate IP resource, adding a reconstruction label for the candidate IP resource, and forming a reconstruction IP resource; in response to an allocation request of a target user, allocating special IP resources to the target user from the transformed IP resources, and configuring a user tag for the special IP resources; and in response to a permission configuration request of the target user, configuring a white list for the special IP resource, so that the target user returns to a source target server according to the special IP resource configured with the white list. According to the technical scheme provided by one or more embodiments of the invention, the content distribution network can be utilized to be compatible with different versions of internet interconnection protocols, and the stability of the back-to-source internet interconnection protocol address can be ensured.

An interface for coupling an agent to a fabric supports a load / store interconnect protocol, where the I / O interconnect protocol includes a flit mode and a non-flit mode. A set of flit mode header formats are used when in the flit mode and a set of non-flit mode header formats are used when in the non-flit mode, the set of non-flit mode header formats including one or more non-flit mode fields. Interface logic determines that a link is trained to the non-flit mode and generates a header according to the set of flit mode header formats, where the header includes a field to indicate that a corresponding packet originated as a non-flit mode packet. One or more fields of the set of flit mode header formats are repurposed in the header to carry the one or more non-flit mode fields before sending the modified header over the interface.

The embodiments of the present application provide a data processing method, device, electronic device and storage medium, which relate to the field of communication technology and can reduce the resource consumption of the processor. The data processing method is used in an electronic device, and the electronic device includes an application processor and an Internet protocol accelerator IPA, and the IPA is used to route and forward data. The data processing method includes: obtaining received data from the IPA; triggering a virtual network card to divert the received data through an interrupt to obtain the diverted received data; and obtaining the diverted received data through a network subsystem in the application processor.

Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC / ECC combinations can be used based on the interconnect protocol and the link operational conditions.

This application provides an availability zone interconnection communication system and method, relating to the field of cloud computing technology. The system includes: multiple first protocol gateway devices, which share one or more Scalable Virtual Local Area Network (VTEP) Internet Protocol IPs; wherein the first protocol gateway devices are used to communicate with second protocol gateway devices based on the VTEP IP; and the second protocol gateway devices are gateway devices of another availability zone interconnection communication system. The solution of this application constructs multiple first protocol gateway devices and communicates with another availability zone interconnection communication system via VTEP IP, which can shield the differences in communication between heterogeneous availability zones.

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

To provide an apparatus in which a link trained in two non-flit modes (NFM) is communicated, and packet integrity is not damaged while simplicity of receiver decode in cut-through routing and flit mode (FM) format is maintained.SOLUTION: An interface for coupling an agent to a fabric supports a load / store interconnect protocol which includes an FM and a NFM. In the case of the FM, a set of FM header formats is used, and in the case of the NFM, a set of NFM header formats is used. Interface logic determines that a link is trained to the NFM, generates a header according to the set of FM header formats. One or more fields of the set of FM header formats are reused in the header to carry the one or more NFM fields before sending the modified header over the interface.SELECTED DRAWING: Figure 14

Systems, methods, and devices may involve a host device including a root complex, a link, and an interconnect protocol stack coupled to the bus link. The interconnect protocol stack may include multiplexing logic and physical layer logic, the multiplexing logic being used to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode or an accelerator link protocol upper layer mode for communicating over the link, and the physical layer logic being used to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

The present application relates to the technical field of communications. Provided are a network connection method and a related product. The method comprises: monitoring a target notification message, wherein the target notification message is used for representing a target fault type that causes an call abnormality in an Internet protocol multimedia subsystem (IMS); and in response to the target notification message, executing a target fault recovery operation on the basis of the target fault type and a preset fault recovery policy, so as to connect a call service network, wherein the fault recovery policy comprises a correspondence between a plurality of fault types and a plurality of fault recovery operations. By means of the method, a call service can be recovered without the perception of a user, thereby improving the user experience.

Method, controller and storage device for information configuration of power mode change of an interconnect protocol. The method is for use in a first device capable of linking a second device according to an interconnect protocol, the method comprising, when a hardware protocol engine of the first device for a protocol layer implementing the interconnect protocol performs a power mode change: generating, by the hardware protocol engine, a configuration indication signal to trigger a firmware of the first device to configure information to a physical layer of the interconnect protocol, wherein the configuration indication signal is non-standard with respect to the interconnect protocol and the firmware is outside the hardware protocol engine; configuring, by the firmware, the physical layer with the information in response to the configuration indication signal; and notifying, by the firmware, the hardware protocol engine of completion of the information configuration upon completion of the information configuration to the physical layer.