14 results about "Interconnect agreement" patented technology

The present application relates to the technical field of data storage, and specifically discloses a data transmission method and device, a heterogeneous system, and a coherent interconnect processing component. The coherent interconnect processing component installed on a device enables corresponding coherent interconnect interfaces on the basis of the number of other devices to be interconnected in a heterogeneous system where said device is located, initializes physical communication links to obtain memory interconnect parameters, establishes memory coherent interconnect communication links between the devices on the basis of the memory interconnect parameters, allocates corresponding cache spaces from said device, and on the basis of the memory coherent interconnect communication links and the cache spaces, performs cache coherent transaction processing of said device and the other devices, so as to implement memory coherent interconnect transmission requests between said device and the other devices. Therefore, topologies can be dynamically sensed, and memory coherent interconnect communication links between devices in a heterogeneous system can be automatically established, thereby mitigating the problem that different device interconnect protocols need to be managed in the heterogeneous system, achieving inter-device cache coherence, and further improving the access performance.

The invention relates to the technical field of chip design, in particular to a high-speed interconnection interface system, which comprises an on-chip interface relay module supporting bidirectional data transmission, an interconnection protocol conversion module and a physical layer processing module, and is characterized in that the on-chip interface relay module is configured to receive an instruction and generate a transaction signal conforming to an on-chip interface protocol specification; the interconnection protocol conversion module is configured to receive a transaction signal, obtain user-defined information, insert the user-defined information into a user field of the transaction signal and package the user-defined information into a data frame conforming to a user-defined transmission protocol specification of the physical layer processing module; wherein the user-defined information carries an address field segment of a physical transmission channel; the physical layer processing module comprises N independent physical transmission channels, wherein N is greater than or equal to 1; each physical transmission channel comprises a sending end, and the sending end is configured to receive the data frame, process the data frame and then send the data frame, so that the purposes of supporting N physical transmission channels and customizing a transmission protocol are achieved.

The invention relates to tunneling of peripheral bus protocol traffic over a consistent fabric and an inter-chip or inter-die bus. A peripheral device includes: a master chip, the master chip including a coherent interconnect; one or more first peripheral bus modules; an inter-chip (C2C) or inter-die (D2D) interface; and one or more tunnel adapters. A coherency interconnect is used to connect electronic components of a peripheral device according to a coherency interconnect protocol. The one or more first peripheral bus modules are configured to communicate according to a peripheral bus protocol. The C2C or D2D interface is to communicate with an auxiliary chip comprising one or more second peripheral bus modules over a C2C or D2D bus. The one or more tunnel adapters are configured to transmit peripheral bus packets of a peripheral bus protocol between the first and second peripheral bus modules over the coherency interconnect and the C2C or D2D bus by transitioning between the peripheral bus packets, messages of the coherency interconnect protocol, and C2C or D2D bus messages.

A control method for error handling in a controller, a storage medium thereof, the controller, and a storage device. The controller is used in a first device capable of linking a second device in accordance with an interconnection protocol. The control method includes the steps of: processing, by the controller, first error information by sending a negative acknowledgement control message to the second device in accordance with the interconnection protocol, wherein the first error information indicates a first error that occurred when the controller performs data reception at a protocol layer in accordance with the interconnection protocol; and setting error handling state data to indicate that error handling is declared for the first error information, so that the controller does not handle a sequence number error that occurs after the first error until the error handling state data is set to indicate that the error handling is undecleared.

Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.

A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.

In one embodiment, an apparatus includes a first die comprising: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry, where the die-to-die adapter is to receive first information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter. The physical layer circuitry is configured to receive and output the first information to a second die via an interconnect and comprises: a first plurality of transmitters to transmit data via a first plurality of data lanes; and at least one redundant transmitter. The physical layer circuitry may be configured to remap a first data lane of the first plurality of data lanes to the at least one redundant transmitter. Other embodiments are described and claimed.

Method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. The method is suitable for an electronic device capable of communicating with another electronic device. The method comprises the following steps. At a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b / 10b encoding. At the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. The test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.

The present invention relates to the field of chip design technology, and in particular to a high-speed interconnection interface system, which includes an on-chip interface relay module supporting bidirectional data transmission, an interconnection protocol conversion module and a physical layer processing module, wherein the on-chip interface relay module is configured to receive instructions and generate transaction signals that comply with the on-chip interface protocol specification; the interconnection protocol conversion module is configured to receive the transaction signal and obtain user-defined information, insert the user-defined information into the user field of the transaction signal and encapsulate it into a data frame that complies with the custom transmission protocol specification of the physical layer processing module; wherein the user-defined information carries the address field of the physical transmission channel; the physical layer processing module includes N independent physical transmission channels, wherein N≥1; each physical transmission channel includes a transmitting end, and the transmitting end is configured to receive a data frame, process it, and then transmit it, thereby achieving the purpose of supporting N physical transmission channels and custom transmission protocols.

Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC / ECC combinations can be used based on the interconnect protocol and the link operational conditions.

This application provides an availability zone interconnection communication system and method, relating to the field of cloud computing technology. The system includes: multiple first protocol gateway devices, which share one or more Scalable Virtual Local Area Network (VTEP) Internet Protocol IPs; wherein the first protocol gateway devices are used to communicate with second protocol gateway devices based on the VTEP IP; and the second protocol gateway devices are gateway devices of another availability zone interconnection communication system. The solution of this application constructs multiple first protocol gateway devices and communicates with another availability zone interconnection communication system via VTEP IP, which can shield the differences in communication between heterogeneous availability zones.

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

Method, controller and storage device for information configuration of power mode change of an interconnect protocol. The method is for use in a first device capable of linking a second device according to an interconnect protocol, the method comprising, when a hardware protocol engine of the first device for a protocol layer implementing the interconnect protocol performs a power mode change: generating, by the hardware protocol engine, a configuration indication signal to trigger a firmware of the first device to configure information to a physical layer of the interconnect protocol, wherein the configuration indication signal is non-standard with respect to the interconnect protocol and the firmware is outside the hardware protocol engine; configuring, by the firmware, the physical layer with the information in response to the configuration indication signal; and notifying, by the firmware, the hardware protocol engine of completion of the information configuration upon completion of the information configuration to the physical layer.