A neural network processing apparatus and a method thereof for performing a matrix vector multiplication instruction

A matrix-vector and processing device technology, applied in the field of communications, can solve the problems that vector operation instructions cannot support sparse neural network sparse vector or sparse matrix operations, high computational overhead, and high energy consumption

Inactive Publication Date: 2018-12-07
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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Problems solved by technology

[0004] However, the existing vector operation instructions cannot support the operations of sparse vectors or sparse matrices in sparse neural networks, let alone the operations of variable-scale sparse vectors or sparse matrices, and the current vector operation instructions can only implem

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  • A neural network processing apparatus and a method thereof for performing a matrix vector multiplication instruction
  • A neural network processing apparatus and a method thereof for performing a matrix vector multiplication instruction
  • A neural network processing apparatus and a method thereof for performing a matrix vector multiplication instruction

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[0100] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0101] The terms "first", "second", "third" and "fourth" in the description and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited ...

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Abstract

The invention provides a processing apparatus comprising a memory, a register unit, an operation unit and a control unit; the memory stores vectors; the register unit stores a matrix vector multiplication instruction; the control unit acquires the matrix vector multiplication instruction; the matrix vector multiplication instruction is analyzed to obtain an operation a code and an operation field;matrix vector multiplication operational data is obtained from the memory according to the operation code; and the operation unit performs matrix vector multiplication on the data participating in the matrix vector multiplication operation. The technical scheme provided by the invention has advantages of low power dissipation and low operational cost.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a neural network processing device and a method for executing matrix-vector multiplication instructions. Background technique [0002] In modern general-purpose and special-purpose processors, more and more calculation instructions (such as vector instructions) are introduced to perform operations. Vector instructions are instructions that enable the processor to perform vector or matrix operations, such as addition and subtraction of vectors, inner product of vectors, matrix multiplication, and matrix convolution. In the vector instruction, at least one input is a vector or a matrix, or the operation result is a vector or a matrix. Vector instructions can perform parallel calculations by calling the vector processing components inside the processor to improve the operation speed. In the existing vector instructions, the vector or matrix in its operand or result is gener...

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Application Information

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IPC IPC(8): G06N3/063G06F17/16
CPCG06F9/3001G06F17/16G06N3/063
Inventor 王秉睿周聖元张尧
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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