A neural network processing apparatus and a method thereof for performing a matrix vector multiplication instruction

Abstract

The invention provides a processing apparatus comprising a memory, a register unit, an operation unit and a control unit; the memory stores vectors; the register unit stores a matrix vector multiplication instruction; the control unit acquires the matrix vector multiplication instruction; the matrix vector multiplication instruction is analyzed to obtain an operation a code and an operation field;matrix vector multiplication operational data is obtained from the memory according to the operation code; and the operation unit performs matrix vector multiplication on the data participating in the matrix vector multiplication operation. The technical scheme provided by the invention has advantages of low power dissipation and low operational cost.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a neural network processing device and a method for executing matrix-vector multiplication instructions. Background technique [0002] In modern general-purpose and special-purpose processors, more and more calculation instructions (such as vector instructions) are introduced to perform operations. Vector instructions are instructions that enable the processor to perform vector or matrix operations, such as addition and subtraction of vectors, inner product of vectors, matrix multiplication, and matrix convolution. In the vector instruction, at least one input is a vector or a matrix, or the operation result is a vector or a matrix. Vector instructions can perform parallel calculations by calling the vector processing components inside the processor to improve the operation speed. In the existing vector instructions, the vector or matrix in its operand or result is gener...

AI Technical Summary

Problems solved by technology

[0004] However, the existing vector operation instructions cannot support the operations of sparse vectors or sparse matrices in sparse neural networks, let alone the operations of variable-scale sparse vectors or sparse matrices, and the current vector operation instructions can only implement one type of operation. For example, one vector instruction can only implement one operation of multiplication and addition, but one vector instruction cannot implement more than two operations, so the existing vector operations have high computational overhead and high energy consumption.

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