LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods
A technology of transistors and vertical gates, applied to LDMOS transistors including vertical gates with multiple dielectric sections and related fields, capable of solving the problems of low n-type dopant concentration and the like
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0066] Applicants have developed LDMOS transistors and related systems and methods that significantly improve upon the prior art. Certain embodiments of LDMOS transistors include a gate dielectric layer formed in the trench of the silicon semiconductor structure to facilitate high transistor performance and small transistor pitch. In some embodiments, the gate dielectric layer includes at least three dielectric segments that separate the vertical gate conductors from the silicon semiconductor structure by different respective separation distances to facilitate low on-resistance and high shock. The wear voltage is both. For example, the number of dielectric segments is determined by the required breakdown voltage and associated on-resistance. Additionally, some embodiments include both vertical and lateral gates.
[0067] figure 2 is a top plan view of LDMOS transistor 200 including a vertical gate with three dielectric segments. image 3 is an LDMOS transistor 200 along ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


