Design method of parallel pseudorandom sequence generator based on FPGA

A pseudo-random sequence and design method technology, applied in the field of pseudo-random sequence generators, can solve the problem that serial pseudo-random sequence generators cannot reach such a high rate, and achieve high clock operation speed, high clock operation frequency, and low occupancy The effect of less logic resources

Pending Publication Date: 2018-12-18
GLORY WIRELESS CO LTD
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Problems solved by technology

[0005] At present, the commonly used pseudo-random sequence generator adopts the serial linear feedback shift register architecture, but with the improvement of wireless communication bandwidth, the communication rate reaches Gbit / s, and the serial pseudo-random sequence generator is far from reaching such a high level. s speed

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  • Design method of parallel pseudorandom sequence generator based on FPGA
  • Design method of parallel pseudorandom sequence generator based on FPGA
  • Design method of parallel pseudorandom sequence generator based on FPGA

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Embodiment Construction

[0021] The present invention will be described below in conjunction with the accompanying drawings.

[0022] like figure 1 and figure 2 The two traditional LFSR structures are shown, and the generated pseudo-random sequence is expressed as: r m-1 (0), r m-1 (1), r m-1 (2), r m-1 (3), r m-1 (4)..., wherein, the pseudo-random sequence output of the Fibonacci LFSR structure can also be expressed as follows: r m-1 (0), r m-2 (0), r m-3 (0)...r 1 (0), r 0 (0), r m-1 (m), r m-2 (m), r m-3 (m)...r 1 (m), r 0 (m)..., that is, at the same time, the Fibonacci LFSR structure can output m continuous pseudo-random sequences in parallel.

[0023] like image 3 as shown,

[0024] Considering w=8-bit parallel output, the output of each D flip-flop at the next moment should be the last wth sampling value of the corresponding serial output. At the i-th moment, the output states of the m D flip-flops in the Fibonacci LFSR structure are exactly w bits and output the first m bi...

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Abstract

The invention relates to the field of digital signal processing, in particular to a pseudorandom sequence generator with selectable parallel bit width and generating polynomial. A design method of a parallel pseudorandom sequence generator based on FPGA is provided. The concrete steps are as follows: one-step shift matrix is obtained by using the generated polynomial; according to one-step shift matrix and initial value, a series of matrix operations are carried out by using MATLAB to obtain the initialization logic and feedback logic of the register group; according to the initialization logic and feedback logic, the hardware logic is built. The generator has the characteristics of arbitrary parallel number, fewer logic resources and high frequency of clock operation.

Description

technical field [0001] The invention relates to the field of digital signal processing, in particular to a pseudo-random sequence generator with optional parallel bit width and generator polynomial. Background technique [0002] Pseudo-random sequence is a definite sequence with certain random characteristics, which has good randomness and a correlation function close to white noise, and has foreseeable determinability and repeatability. These characteristics make pseudo-random sequences widely used in important technical fields such as communication, radar, navigation and cryptography. The regular randomness of pseudo-random sequence makes it widely used as spreading code and scrambling code in wireless communication. [0003] Nowadays, the research on pseudo-random sequences is divided into two categories: one is multi-bit pseudo-random sequence generators. The other is a 1-bit pseudo-random sequence generator, and the pseudo-random sequences used in spreading codes and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/327G06F30/331
Inventor 吕启福罗志刚
Owner GLORY WIRELESS CO LTD
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