A Shift-Based Instruction Fetching and Buffering Method and Superscalar Microprocessor

Abstract

The invention discloses a shift-based instruction extraction and buffering method and a superscalar microprocessor. The implementation steps of the extraction and buffering method include constructing an effective word mask for the instruction word, and right-aligning the instruction line according to the instruction word offset According to the effective word mask, split the shifted instruction line according to the word width and extract the effective words, sort the effective words into the buffer block sequence, and write the buffer block sequence into the buffer queue according to the write enable control of the buffer item ; The superscalar microprocessor includes an instruction fetch and buffer logic unit programmed to perform the aforementioned instruction fetch and buffer method. The invention adopts the design of command line shifting, command word sorting and buffer block sequence writing into the buffer queue, which is simpler and easier to implement than the traditional logic, can ensure the high efficiency of fetching, and also makes the extraction logic and buffer logic more efficient. For simplicity, the hardware overhead is reduced.

Description

technical field [0001] The invention relates to the field of microprocessors, in particular to a shift-based instruction extraction and buffering method and a superscalar microprocessor. Background technique [0002] A superscalar microprocessor can send multiple instructions to each execution unit per cycle to increase the total processing capacity of the processor. This requires the instruction fetch unit and decoding unit at the front end of the microprocessor pipeline to efficiently provide instruction streams to execution unit. Therefore, the instruction fetch unit of the microprocessor must have a corresponding logic circuit to process the instruction byte stream entering the pipeline, determine the start boundary of the instruction word and extract the effective instruction word, so that it can enter the decoding unit or instruction word as soon as possible. buffer queue. [0003] In processor design, the traditional technology is to extract and buffer effective ins...

AI Technical Summary

Problems solved by technology

The difficulty is that the number of effective instructions is not fixed, and cannot be processed in a fixed way when fetching and buffering, resulting in relatively complicated selection logic

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