Isolation manufacturing method for semiconductor structures

Abstract

A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

Description

technical field [0001] Embodiments of the invention relate to semiconductor structures and methods of fabricating the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During IC evolution, functional density (ie, the number of interconnected devices per chip area) typically increases, while geometry size (ie, the smallest component (or line) that can be produced using a fabrication process) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. [0003] For example, mu...

AI Technical Summary

Problems solved by technology

However, fabrication of HGAA transistors can be challenging

For example, epitaxially growing a stack of semiconductor materials for HGAA transistors to form channels by current methods is not satisfactory in all respects, especially at smaller device pitches, then 40 nanometers (nm) or less.

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