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NVM test acceleration method and system

A technology for accelerating systems and operating instructions, applied in static memory, instruments, etc., can solve the problem of NVM taking a long time, and achieve the effect of improving test efficiency, reducing test cost, and reducing test time

Active Publication Date: 2021-01-22
BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY +3
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a method for accelerating NVM testing, which can solve the problem that the reading and writing operations of NVM take a long time during chip testing

Method used

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  • NVM test acceleration method and system
  • NVM test acceleration method and system

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Embodiment Construction

[0020] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0021] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

[0022] As shown in Figure 1, the NVM test acceleration method of a preferred embodiment of the present invention includes the following steps: Step 101: enter the first NVM operation instruction through the test command, wherein the first NVM operation instruction includes data and address information; Step 102 : Decoding and processing the first NVM operation instruction to extract data and address information; Step 103: B...

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Abstract

The invention discloses an NVM test acceleration method and a system. The NVM test acceleration method comprises the following steps: a first NVM operation instruction being inputted through a test command, wherein, the first NVM operation instruction comprises data and address information; decoding and processing the first NVM operation instruction to extract data and address information; generating a first control signal satisfying timing information of erase, write and read operations of the NVM memory based on a first NVM operation instruction, wherein the first control signal is selectedto control a plurality of NVM memories in parallel based on the first NVM operation instruction; based on the first control signal and according to the data and the address, the corresponding operation of the NVM memory being carried out and the output data being generated; and comparing the output data based on the first NVM operation instruction and outputting a failure signal representing the comparison result. The NVM test acceleration method of the invention can greatly reduce the test time, thereby reducing the test cost and remarkably improving the test efficiency.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to an NVM testing acceleration method and system. Background technique [0002] Testing plays a very important role in the manufacturing process of integrated circuit products. From the time the chip is processed and manufactured to the hand of the end user, it has gone through many different tests to ensure the quality of the product. With the advancement of semiconductor process technology and the increase of design complexity, it has had a huge impact on the cost of chip testing. The longer the test time, the longer the production time of the chip, and the higher the test cost, thus greatly increasing the cost of the whole chip. As the capacity of NVM type memory increases, the NVM test time also increases accordingly. As the main method for judging whether the NVM stored data is correct, the time required for data reading and comparison also increases significantly. T...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56004
Inventor 吕品关媛张海峰唐晓柯袁远东邵明驰
Owner BEIJING SMARTCHIP MICROELECTRONICS TECH COMPANY