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Semiconductor device with liner layer with configurable profile and manufacturing method thereof

A semiconductor and liner layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as reducing fin pitch and limitations

Active Publication Date: 2021-11-30
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Specifically, reducing fin pitch and increasing fin height significantly limits the capability of existing processes for forming contact features to source and drain or gate features of FinFET devices

Method used

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  • Semiconductor device with liner layer with configurable profile and manufacturing method thereof
  • Semiconductor device with liner layer with configurable profile and manufacturing method thereof
  • Semiconductor device with liner layer with configurable profile and manufacturing method thereof

Examples

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Embodiment Construction

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component on or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component. components so that the first component and the second component may not be in direct contact with each other.

[0015] In addition, the present invention may repeat reference numerals and / or characters in various embodiments. This repetition is for the sake of simplicity and clarity and does not in itself indic...

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PUM

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Abstract

Devices and methods include contouring a pad layer prior to filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness at the top of the opening, the second thickness being less than the first thickness. In an embodiment, the filled opening provides a contact structure. Embodiments of the present invention also relate to semiconductor devices having a configurable profile pad layer and methods of manufacturing the same.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor device having a liner layer with a configurable profile and a method of manufacturing the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased, while geometry size (ie, the smallest component (or line) that can be produced using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. [0003] This scaling down increases the complexity of handling and manufacturing ICs, and similar developments in IC processing ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823431H01L27/0886H01L23/485H01L21/823821H01L29/785H01L27/0924H01L29/66795H01L21/76846H01L21/76865H01L21/28518H01L21/76855H01L21/76816H01L21/76831H01L29/7855H01L21/76805H01L21/76843H01L23/535H01L21/76895H01L29/7851H01L23/53266H01L21/76889
Inventor 谢彦莹陈华丰
Owner TAIWAN SEMICON MFG CO LTD