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Chip packaging method and chip packaging structure

A chip packaging structure and chip packaging technology, which is applied to semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve bottlenecks and other problems, and achieve the effects of avoiding warping, maintaining heat preservation, and solving high-flow bottlenecks

Active Publication Date: 2020-08-28
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

CoW packaging technology has many advantages, such as the ability to achieve high integration of semiconductor devices, reduce the size of semiconductor packages, reduce the cost of final products, simplify the assembly process and improve yield, etc., but the packaging technology is currently achieving high throughput ( High Throughput) has a bottleneck in Die Stacking

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  • Chip packaging method and chip packaging structure
  • Chip packaging method and chip packaging structure
  • Chip packaging method and chip packaging structure

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Embodiment Construction

[0033] The key processes in a CoW packaging technology include Device Wafer Backside Grinding, Die Stacking and Die Saw. Among them, the main purpose of the backside thinning process of the component wafer is The Through Silicon Via (TSV) structure in the component wafer is exposed from the back side of the component wafer. After the backside thinning process of the component wafer is completed, the component wafer after the backside thinning needs to be pasted on the A carrier wafer (Carrier Wafer or Silicon Carrier) for support (Support), and then subsequent chip stacking (Die Stacking) on ​​the component wafer, and then transferred to a dicing tape machine (DicingTape) for wafer dicing (Die Saw). Since the thinned component wafer on the back becomes very thin, it is called Ultra-Thin Wafer or Thin Wafer, usually 50um, and it is prone to serious warpage (Warpage) when it is transferred to the carrier wafer. At the same time, Due to the high thermal conductivity of the carri...

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Abstract

the invention provides a chip packaging method and a chip packaging structure. The method comprises the following steps: a dry film layer having an air gap structure is formed on the front surface ofthe element wafer to thicken the element wafer, thereby supporting the element wafer during the thinning process of the back surface of the element wafer and during the thinning process of the transfer element wafer, facilitating operation of the element wafer and avoiding warpage of the element wafer; Secondly, in the subsequent wafer stacking process, the air thermal conductivity in the air gapof the dry film layer is lower than that of the carrier, so that the heat is kept well, and the problem of high flux bottleneck caused by the high thermal conductivity of the carrier is solved. In addition, the dry film molding mainly adopts the process of sticking film, exposure, development and so on, and the time is short, which has little influence on the whole packaging time.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a chip packaging method and a chip packaging structure. Background technique [0002] Chip on wafer (CoW) packaging technology, as one of the advanced packaging (Package) technologies, can stack multiple chips separately on the positions of good chips that are pre-identified on a device wafer (Device Wafer) (Die, that is, a block with complete functions cut out from the wafer), to realize the manufacture of three-dimensional semiconductor integrated circuit chips (IC). CoW packaging technology has many advantages, such as the ability to achieve high integration of semiconductor devices, reduce the size of semiconductor packages, reduce the cost of final products, simplify the assembly process and improve yield, etc., but the packaging technology is currently achieving high throughput ( High Throughput) die stacking (Die Stacking) has a bottleneck. Cont...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L23/31
CPCH01L21/568H01L23/31
Inventor 陈彧
Owner SEMICON MFG INT (SHANGHAI) CORP