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Parallel structure and manufacturing method thereof, and electronic device comprising parallel structure

A parallel and conductive channel technology, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of difficulty in forming transistor interconnections, achieve the effects of saving area, reducing occupied area, and eliminating offset

Active Publication Date: 2019-02-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the formation of interconnections between transistors is difficult

Method used

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  • Parallel structure and manufacturing method thereof, and electronic device comprising parallel structure
  • Parallel structure and manufacturing method thereof, and electronic device comprising parallel structure
  • Parallel structure and manufacturing method thereof, and electronic device comprising parallel structure

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Embodiment Construction

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0012] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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Abstract

The present invention discloses a parallel structure and a manufacturing method thereof, and an electronic device comprising a parallel structure. The parallel structure comprises source / drain layersand channel layers alternately stacked on a substrate and a gate stack formed by winding at least part of the periphery of each channel layer. Each channel layer, the source / drain layers at the upperand lower sides and the gate stack formed through winding form corresponding semiconductor devices. In each semiconductor device, one of the source / drain layers at the upper and lower sides of the corresponding channel layers is in contact with a first conductive channel arranged at the periphery of an active region, the other one of the source / drain layers is in contact with a second conductive channel arranged at the periphery of the active region, and the gate stack formed by winding the channel layers is in contact with a third conductive channel arranged at the periphery of the active region. The first conductive channel is common for all the semiconductor devices, the second conductive channel is common for all the semiconductor devices, and the third conductive channel is common forall the semiconductor devices.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and more particularly, to a compact parallel structure of a semiconductor device, a method of manufacturing the same, and an electronic device including such a parallel structure. Background technique [0002] Vertical devices have good device characteristics, such as good electrostatic properties, good control of short channel effects, small sub-threshold swing, and resulting low power consumption. This enables further scaling of the device to increase integration density. In some applications it is necessary to connect several transistors in parallel, for example in order to obtain a large drive current to drive other devices. These transistors can be stacked vertically to save area. However, the formation of interconnections between transistors is difficult. Contents of the invention [0003] In view of this, it is an object of the present disclosure to provide, at least in part, a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/52H01L21/77
CPCH01L23/52H01L21/77H01L27/088H01L29/7827H01L29/7391H01L29/66666H01L29/66356H01L29/66545H01L29/41741H01L29/0653H01L29/78642H01L21/8221H01L21/823487H01L21/823418H01L27/0688H01L25/0657H01L25/50H01L29/66712H01L29/7802
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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