Bidirectional interlayer isolation well with low power consumption and high reliability

Abstract

The present invention provides a bidirectional interlayer isolation well with low power consumption and high reliability. The bidirectional interlayer isolation well comprises a substrate and a longitudinal isolation well region and a first buried layer arranged on the substrate, the first buried layer is arranged around the longitudinal isolation well region, the longitudinal isolation well region is provided with a first well region and a transverse isolation well region, the transverse isolation well region is arranged around a first well region, a second well region is arranged on the first buried layer and arranged around the transverse isolation well region, the first well region, the transverse isolation well region and the second well region commonly form two transverse PNP structures, the first well region, the longitudinal isolation well region and the substrate commonly form two longitudinal PNP structures, when the first well region encounters a high voltage, the two transverse PNPs and the two longitudinal PNPs cannot be subjected to amplification and bias due to the same-potential arrangement of the transverse isolation well region so as to effectively weaken the leakage currents in horizontal and vertical directions. The bidirectional interlayer isolation well with low power consumption and high reliability is scientific in design, high in isolation, low in reverse leakage and high in reliability.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a bidirectional interlayer isolation well with low power consumption and high reliability. Background technique [0002] At present, the conventional PN junction reverse biased well isolation structure on the integrated circuit process platform is as follows: figure 1 As shown, a substrate 101 of the second conductivity type is included, a buried layer 103 of the first conductivity type is formed on the substrate 101 of the second conductivity type, and a well region 106 of the second conductivity type is formed on the buried layer 103, A well region 107 of the first conductivity type is formed on the periphery of the well region 106 of the second conductivity type, and the bottom of the well region 107 of the first conductivity type is connected with the buried layer 103 below to form a hermetic isolation region of the first conductivity type; A buried layer 102 of a second conduc...

AI Technical Summary

Problems solved by technology

Current leakage will occur in the functional circuits in the well region 106, for example, the efficiency of the boost converter circuit will be greatly reduced, the boost converter circuit will be limited, and the current leakage will increase the latch up (Latchup refers to the cmos chip, in the power supply The risk of a low-impedance path between VDD and ground GND due to the interaction of parasitic PNP and NPN bipolar BJTs) reduces the reliability of the chip

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