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Package structure and packaging method of semiconductor device

A package structure and packaging method technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as poor anti-warping performance, suppress warping deformation, and reduce quality hidden dangers , the effect of improving stability

Active Publication Date: 2020-07-24
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a package structure and a packaging method of a semiconductor device, which are used to solve the problem of poor warpage resistance after packaging of the existing semiconductor device

Method used

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  • Package structure and packaging method of semiconductor device
  • Package structure and packaging method of semiconductor device
  • Package structure and packaging method of semiconductor device

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Embodiment Construction

[0043] The specific implementation of the package structure and semiconductor device packaging method provided by the present invention will be described in detail below in conjunction with the accompanying drawings.

[0044] The package structure formed by encapsulating the semiconductor device is sequentially provided with a plastic encapsulation layer, a semiconductor device, a package substrate and a solder ball array along the vertical direction from the top to the bottom. Generally speaking, the thermal expansion coefficient of the packaging substrate is about 10, the thermal expansion coefficient of the semiconductor device (or silicon chip) is about 2.4, and the thermal expansion coefficient of the plastic sealing layer changes with the change of the ambient temperature, for example, the thermal expansion of the plastic sealing layer at room temperature The coefficient is 9 or 10, and the thermal expansion coefficient of the plastic sealing layer can reach about 36 at a...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a package structure and a package method for a semiconductor device. The package structure includes: a packaging substrate, suitable for carrying a semiconductor device; a plastic sealing layer, covering the surface of the packaging substrate and plastic sealing the semiconductor device; an adjustment layer, suitable for covering the surface of the plastic sealing layer away from the packaging substrate , and the difference in coefficient of thermal expansion between the adjustment layer and the packaging substrate is smaller than a threshold value, so as to prevent the package structure from warping in a direction perpendicular to the packaging substrate. The invention suppresses the warping deformation of the packaging body structure, improves the performance stability of the packaged semiconductor device, and reduces the quality hidden danger of the customer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a package structure and a package method for a semiconductor device. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Among them, 3D NAND memory takes its small size and large capacity as the starting point, and the design concept of highly integrated storage units stacked in three-di...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/29H01L21/56
CPCH01L21/56H01L23/29H01L23/3135H01L2224/32145H01L2224/48145H01L2224/73265H01L2924/181H01L2924/15311H01L2924/00012H01L2924/00
Inventor 陈鹏周厚德张保华周俊徐震
Owner YANGTZE MEMORY TECH CO LTD